!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME	Exuberant Ctags	//
!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
!_TAG_PROGRAM_VERSION	5.9~svn20110310	//
ADDR_HI	include/pedd_xdata.h	/^   UINT32           ADDR_HI;   \/\/ 0x04$/;"	m	struct:_XDATA_REGISTERS
ADDR_LO	include/pedd_xdata.h	/^   UINT32           ADDR_LO;   \/\/ 0x00$/;"	m	struct:_XDATA_REGISTERS
AT	include/pedd_dma.h	/^        UINT32      AT          :2;    \/\/ 30:31$/;"	m	struct:__anon22::__anon23
AbortClr	include/pedd_dma.h	/^        UINT32      AbortClr    :8;$/;"	m	struct:__anon16::__anon17
AbortIntrCnt	include/pedd_hal_dma.h	/^    UINT32 AbortIntrCnt;$/;"	m	struct:__anon41
AbortSta	include/pedd_dma.h	/^        UINT32      AbortSta    :8;$/;"	m	struct:__anon14::__anon15
AllocProtocolMem	pedd.c	/^static UINT32 AllocProtocolMem(struct pedd_dev *priv, UINT32 memSize, PUINT32 *pvaddr, dma_addr_t *dma_bus, PHYADDR *ppaddr)$/;"	f	file:
AsDword	include/pedd_dma.h	/^    UINT32  AsDword;$/;"	m	union:__anon28
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon10
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon12
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon14
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon16
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon18
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon20
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon22
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon24
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon30
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon32
AsDword	include/pedd_dma.h	/^    UINT32 AsDword;$/;"	m	union:__anon8
AsDword	include/pedd_perf.h	/^    UINT32 AsDword;$/;"	m	union:__anon49
AsUint32	include/pedd_xdata.h	/^    UINT32 AsUint32;$/;"	m	union:_XDATA_CTRL
AsUint32	include/pedd_xdata.h	/^    UINT32 AsUint32;$/;"	m	union:_XDATA_STATUS
BAR_MEM	include/pedd.h	25;"	d
BIG_COUNTER	include/pedd_perf.h	/^} BIG_COUNTER;$/;"	t	typeref:union:__anon51
BIST	include/pedd_types.h	/^    UCHAR   BIST;                       \/\/ Built in self test$/;"	m	struct:_PCI_COMMON_CONFIG
BOOL	include/pedd_types.h	/^typedef int                 BOOL;$/;"	t
BOOLEAN	include/pedd_types.h	/^typedef BYTE                BOOLEAN;$/;"	t
BUILDSYSTEM_DIR	Makefile	/^	BUILDSYSTEM_DIR:=\/lib\/modules\/$(shell uname -r)\/build$/;"	m
BURSTS	include/pedd_xdata.h	/^   UINT32           BURSTS;    \/\/ 0x28$/;"	m	struct:_XDATA_REGISTERS
BURST_CNT	include/pedd_xdata.h	/^   UINT32           BURST_CNT; \/\/ 0x08$/;"	m	struct:_XDATA_REGISTERS
BYTE	include/pedd_types.h	/^typedef unsigned char       BYTE;$/;"	t
Bar	include/pedd_types.h	/^    ULONG    Bar;$/;"	m	struct:_PciBar_GetDataByOffset_USER_IN
Bar	include/pedd_types.h	/^    ULONG    Bar;$/;"	m	struct:_PciBar_SetDataByOffset_USER_IN
BaseAddresses	include/pedd_types.h	/^            ULONG   BaseAddresses[PCI_TYPE0_ADDRESSES];$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
BaseClass	include/pedd_types.h	/^    UCHAR   BaseClass;                  \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG
BatchAllocDmaMem	pedd.c	/^static UINT32 BatchAllocDmaMem(struct pedd_dev *priv, int wrChans, int rdChans)$/;"	f	file:
BlockSize	include/pedd.h	/^	UINT32 BlockSize;   	 \/**< Block size *\/$/;"	m	struct:__anon39
BrdgErr	include/pedd_dma.h	/^        UINT32      BrdgErr     :8;$/;"	m	struct:__anon18::__anon19
CB	include/pedd_dma.h	/^        UINT32      CB          :1;    \/\/ 0$/;"	m	struct:__anon22::__anon23
CCS	include/pedd_dma.h	/^        UINT32      CCS         :1;    \/\/ 8$/;"	m	struct:__anon22::__anon23
CHAN_CTRL_HI	include/pedd_dma.h	/^} CHAN_CTRL_HI;$/;"	t	typeref:union:__anon24
CHAN_CTRL_LO	include/pedd_dma.h	/^} CHAN_CTRL_LO;$/;"	t	typeref:union:__anon22
CHAN_HALTED	include/pedd_dma.h	/^    CHAN_HALTED,        \/**< Channel is halted *\/$/;"	e	enum:__anon6
CHAN_INFO	include/pedd_hal_dma.h	/^} CHAN_INFO, *PCHAN_INFO;$/;"	t	typeref:struct:__anon41
CHAN_INFO_EX	include/pedd.h	/^} CHAN_INFO_EX, *PCHAN_INFO_EX;$/;"	t	typeref:struct:__anon39
CHAN_QUEUING	include/pedd_dma.h	/^    CHAN_QUEUING	    \/**< Queuing. Not a real HW status *\/$/;"	e	enum:__anon6
CHAN_RUNNING	include/pedd_dma.h	/^    CHAN_RUNNING,       \/**< Channel is running *\/$/;"	e	enum:__anon6
CHAN_STOPPED	include/pedd_dma.h	/^    CHAN_STOPPED,       \/**< Channel is stopped *\/$/;"	e	enum:__anon6
CHAN_UNKNOWN	include/pedd_dma.h	/^    CHAN_UNKNOWN = 0,   \/**< Unknown *\/$/;"	e	enum:__anon6
CHAR	include/pedd_types.h	/^typedef char                CHAR;$/;"	t
CHUNK_ID	include/pedd.h	/^} CHUNK_ID;$/;"	t	typeref:enum:__anon35
CHUNK_ID_DDR_R0	include/pedd.h	/^	CHUNK_ID_DDR_R0$/;"	e	enum:__anon35
CHUNK_ID_DDR_W0	include/pedd.h	/^	CHUNK_ID_DDR_W0,$/;"	e	enum:__anon35
CHUNK_ID_LLA	include/pedd.h	/^	CHUNK_ID_LLA,$/;"	e	enum:__anon35
CHUNK_ID_LLB	include/pedd.h	/^	CHUNK_ID_LLB,$/;"	e	enum:__anon35
CHUNK_ID_LLC	include/pedd.h	/^	CHUNK_ID_LLC,$/;"	e	enum:__anon35
CHUNK_ID_LLD	include/pedd.h	/^	CHUNK_ID_LLD,$/;"	e	enum:__anon35
CHUNK_ID_R0	include/pedd.h	/^	CHUNK_ID_R0,$/;"	e	enum:__anon35
CHUNK_ID_R1	include/pedd.h	/^	CHUNK_ID_R1,$/;"	e	enum:__anon35
CHUNK_ID_R2	include/pedd.h	/^	CHUNK_ID_R2,$/;"	e	enum:__anon35
CHUNK_ID_R3	include/pedd.h	/^	CHUNK_ID_R3,$/;"	e	enum:__anon35
CHUNK_ID_R4	include/pedd.h	/^	CHUNK_ID_R4,$/;"	e	enum:__anon35
CHUNK_ID_R5	include/pedd.h	/^	CHUNK_ID_R5,$/;"	e	enum:__anon35
CHUNK_ID_R6	include/pedd.h	/^	CHUNK_ID_R6,$/;"	e	enum:__anon35
CHUNK_ID_R7	include/pedd.h	/^	CHUNK_ID_R7,$/;"	e	enum:__anon35
CHUNK_ID_RSV0	include/pedd.h	/^	CHUNK_ID_RSV0 = 0x1F, \/\/ RESERVED IDs 0x15 - 0x1F$/;"	e	enum:__anon35
CHUNK_ID_W0	include/pedd.h	/^	CHUNK_ID_W0,$/;"	e	enum:__anon35
CHUNK_ID_W1	include/pedd.h	/^	CHUNK_ID_W1,$/;"	e	enum:__anon35
CHUNK_ID_W2	include/pedd.h	/^	CHUNK_ID_W2,$/;"	e	enum:__anon35
CHUNK_ID_W3	include/pedd.h	/^	CHUNK_ID_W3,$/;"	e	enum:__anon35
CHUNK_ID_W4	include/pedd.h	/^	CHUNK_ID_W4,$/;"	e	enum:__anon35
CHUNK_ID_W5	include/pedd.h	/^	CHUNK_ID_W5,$/;"	e	enum:__anon35
CHUNK_ID_W6	include/pedd.h	/^	CHUNK_ID_W6,$/;"	e	enum:__anon35
CHUNK_ID_W7	include/pedd.h	/^	CHUNK_ID_W7,$/;"	e	enum:__anon35
CHUNK_ID_XDATA	include/pedd.h	/^	CHUNK_ID_XDATA,$/;"	e	enum:__anon35
CIS	include/pedd_types.h	/^            ULONG   CIS;$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
CMD_INFO	include/pedd.h	/^} CMD_INFO, *PCMD_INFO;$/;"	t	typeref:struct:__anon40
CONFIG_MODULE_SIG	Makefile	/^CONFIG_MODULE_SIG=n$/;"	m
CTRL	include/pedd_xdata.h	/^   XDATA_CTRL       CTRL;      \/\/ 0x0c$/;"	m	struct:_XDATA_REGISTERS
CTX_GRP	include/pedd_dma.h	/^} CTX_GRP;$/;"	t	typeref:struct:__anon27
CTX_REGS	include/pedd_dma.h	/^} CTX_REGS;$/;"	t	typeref:struct:__anon26
CTX_SEL	include/pedd_dma.h	/^} CTX_SEL;$/;"	t	typeref:union:__anon28
CaErr	include/pedd_dma.h	/^        UINT32      CaErr       :8;$/;"	m	struct:__anon20::__anon21
CacheLineSize	include/pedd_types.h	/^    UCHAR   CacheLineSize;              \/\/ (ro+)$/;"	m	struct:_PCI_COMMON_CONFIG
CapabilitiesPtr	include/pedd_types.h	/^			UCHAR   CapabilitiesPtr;$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
Chan	include/pedd.h	/^	UINT8 Chan;         \/**< Channel number. Value can be 0 to 7. *\/$/;"	m	struct:__anon40
Chan	include/pedd_hal_dma.h	/^    UINT8 Chan;$/;"	m	struct:__anon44
CheckData	pedd.c	/^static BOOLEAN CheckData(PDEVICE_EXTENSION pDevExt, DMA_DIRC dirc, UINT8 chan)$/;"	f	file:
Chk	include/pedd.h	/^	BOOLEAN Chk;        \/**< Check data or not after the transfer *\/$/;"	m	struct:__anon40
Chnl	include/pedd_dma.h	/^        UINT32      Chnl        :3;  \/\/ 0$/;"	m	struct:__anon12::__anon13
ChunkLen	include/pedd.h	/^	UINT32 ChunkLen;           \/**< Length of memory chunk for each channel *\/$/;"	m	struct:_DEVICE_EXTENSION
Cmd	include/pedd.h	/^	DMA_CMD Cmd;        \/**< Command *\/$/;"	m	struct:__anon40
Command	include/pedd_types.h	/^    USHORT  Command;                    \/\/ Device control$/;"	m	struct:_PCI_COMMON_CONFIG
CtrlHi	include/pedd_dma.h	/^    CHAN_CTRL_HI    CtrlHi;     \/\/ 0x04$/;"	m	struct:__anon26
CtrlLo	include/pedd_dma.h	/^    CHAN_CTRL_LO    CtrlLo;     \/\/ 0x00$/;"	m	struct:__anon26
CtxRegs	include/pedd_dma.h	/^    CTX_REGS        CtxRegs;        \/\/ 0xA70 - 0xA90$/;"	m	struct:DMA_REGS
CtxRegsGrp	include/pedd_dma.h	/^    CTX_GRP       CtxRegsGrp[8];$/;"	m	struct:DMA_REGS
CtxRegs_RD	include/pedd_dma.h	/^    CTX_REGS        CtxRegs_RD;$/;"	m	struct:__anon27
CtxRegs_WR	include/pedd_dma.h	/^    CTX_REGS        CtxRegs_WR;$/;"	m	struct:__anon27
CtxSel	include/pedd_dma.h	/^    CTX_SEL         CtxSel;         \/\/ 0xA6C$/;"	m	struct:DMA_REGS
DATA_CHECK_FAILURE	include/pedd.h	/^	DATA_CHECK_FAILURE, \/**< Data check is failed *\/$/;"	e	enum:__anon37
DATA_CHECK_NONE	include/pedd.h	/^	DATA_CHECK_NONE,    \/**< No data check need to be performed *\/$/;"	e	enum:__anon37
DATA_CHECK_READY	include/pedd.h	/^	DATA_CHECK_READY,   \/**< Transfer is finished, ready to be checked. *\/$/;"	e	enum:__anon37
DATA_CHECK_SUCCESS	include/pedd.h	/^	DATA_CHECK_SUCCESS  \/**< Data check is successful *\/$/;"	e	enum:__anon37
DATA_CHECK_UNKNOWN	include/pedd.h	/^	DATA_CHECK_UNKNOWN, \/**< Transfer is running, so the result is unknown *\/$/;"	e	enum:__anon37
DBELL	include/pedd_xdata.h	/^        UINT32      DBELL     :1;  \/\/ 0$/;"	m	struct:_XDATA_CTRL::__anon47
DEFAULT_PATTERN	include/pedd.h	36;"	d
DEPRINTF	include/pedd_dfx.h	42;"	d
DEVICE_EXTENSION	include/pedd.h	/^} DEVICE_EXTENSION, *PDEVICE_EXTENSION;$/;"	t	typeref:struct:_DEVICE_EXTENSION
DMARegGap_1	include/pedd_dma.h	/^    UINT32	    DMARegGap_1[55];$/;"	m	struct:__anon27
DMARegGap_2	include/pedd_dma.h	/^    UINT32	    DMARegGap_2[55];$/;"	m	struct:__anon27
DMA_CHAN_BUSY	include/pedd_hal_dma.h	/^    DMA_CHAN_BUSY,         \/**< Channel is busy to respond *\/$/;"	e	enum:__anon43
DMA_CHAN_DDR	include/pedd.h	/^	DMA_CHAN_DDR         \/**< Local Buffer on DDR *\/$/;"	e	enum:__anon38
DMA_CHAN_END	include/pedd.h	/^} DMA_CHAN_END;$/;"	t	typeref:enum:__anon38
DMA_CHAN_HST	include/pedd.h	/^	DMA_CHAN_HST = 0,    \/**< Host PC Buffer *\/$/;"	e	enum:__anon38
DMA_CHAN_LOC	include/pedd.h	/^	DMA_CHAN_LOC,        \/**< Local Buffer on FPGA *\/$/;"	e	enum:__anon38
DMA_CHAN_STATUS	include/pedd_dma.h	/^} DMA_CHAN_STATUS;$/;"	t	typeref:enum:__anon6
DMA_CMD	include/pedd.h	/^} DMA_CMD;$/;"	t	typeref:enum:__anon36
DMA_CMD_ABORT	include/pedd.h	/^	DMA_CMD_ABORT,      \/**< Abort undergoing DMA transfer *\/$/;"	e	enum:__anon36
DMA_CMD_DQF	include/pedd.h	/^	DMA_CMD_DQF,        \/**< Flush queuing DMA jobs *\/$/;"	e	enum:__anon36
DMA_CMD_DR	include/pedd.h	/^	DMA_CMD_DR,         \/**< DMA read *\/$/;"	e	enum:__anon36
DMA_CMD_DW	include/pedd.h	/^	DMA_CMD_DW,         \/**< DMA write *\/$/;"	e	enum:__anon36
DMA_CMD_INIT	include/pedd.h	/^	DMA_CMD_INIT,       \/**< DMA Initialization *\/$/;"	e	enum:__anon36
DMA_CMD_LLDUMP	include/pedd.h	/^	DMA_CMD_LLDUMP,     \/**< Dump linked list elements *\/$/;"	e	enum:__anon36
DMA_CMD_MADDR	include/pedd.h	/^	DMA_CMD_MADDR,      \/**< Get addresses allocated for DMA device *\/$/;"	e	enum:__anon36
DMA_CMD_MDUMP	include/pedd.h	/^	DMA_CMD_MDUMP,      \/**< Dump buffers *\/$/;"	e	enum:__anon36
DMA_CMD_PERF	include/pedd.h	/^	DMA_CMD_PERF,$/;"	e	enum:__anon36
DMA_CMD_RDUMP	include/pedd.h	/^	DMA_CMD_RDUMP,      \/**< Dump DMA registers address and data of interest *\/$/;"	e	enum:__anon36
DMA_CMD_RESUME	include/pedd.h	/^	DMA_CMD_RESUME,     \/**< Resume stopped DMA transfer *\/$/;"	e	enum:__anon36
DMA_CMD_STATE	include/pedd.h	/^	DMA_CMD_STATE,      \/**< Get channel state *\/$/;"	e	enum:__anon36
DMA_CMD_STOP	include/pedd.h	/^	DMA_CMD_STOP,       \/**< Stop undergoing DMA transfer *\/$/;"	e	enum:__anon36
DMA_CMD_XPERF	include/pedd.h	/^	DMA_CMD_XPERF,	    \/**< Get xData Performance data *\/$/;"	e	enum:__anon36
DMA_CMD_XSTART	include/pedd.h	/^	DMA_CMD_XSTART,     \/**< Start xData transmission *\/$/;"	e	enum:__anon36
DMA_CMD_XSTATUS	include/pedd.h	/^	DMA_CMD_XSTATUS,    \/**< Get xData xfer status *\/$/;"	e	enum:__anon36
DMA_CMD_XSTOP	include/pedd.h	/^	DMA_CMD_XSTOP,      \/**< Stop xData transmission *\/$/;"	e	enum:__anon36
DMA_CS	include/pedd_dma.h	/^        UINT32      DMA_CS      :2;    \/\/ 5:6$/;"	m	struct:__anon22::__anon23
DMA_CTRL	include/pedd_dma.h	/^} DMA_CTRL;$/;"	t	typeref:union:__anon10
DMA_DATA_CHECK	include/pedd.h	/^} DMA_DATA_CHECK;$/;"	t	typeref:enum:__anon37
DMA_DIRC	include/pedd_dma.h	/^} DMA_DIRC;$/;"	t	typeref:enum:__anon3
DMA_ERR	include/pedd_dma.h	/^} DMA_ERR;$/;"	t	typeref:enum:__anon7
DMA_ERR_CODE_NUM	include/pedd_hal_dma.h	/^    DMA_ERR_CODE_NUM       \/**< HAL return code numbers *\/$/;"	e	enum:__anon43
DMA_ERR_COMPLETER_ABORT	include/pedd_dma.h	/^    DMA_ERR_COMPLETER_ABORT,$/;"	e	enum:__anon7
DMA_ERR_CPL_TIME_OUT	include/pedd_dma.h	/^    DMA_ERR_CPL_TIME_OUT,$/;"	e	enum:__anon7
DMA_ERR_DATA_POISONING	include/pedd_dma.h	/^    DMA_ERR_DATA_POISONING,$/;"	e	enum:__anon7
DMA_ERR_FETCH_LL	include/pedd_dma.h	/^    DMA_ERR_FETCH_LL,   \/**< The DMA Write\/Read Channel has received an error$/;"	e	enum:__anon7
DMA_ERR_NONE	include/pedd_dma.h	/^    DMA_ERR_NONE,       \/**< No DMA error found *\/$/;"	e	enum:__anon7
DMA_ERR_RD	include/pedd_dma.h	/^    DMA_ERR_RD,         \/**< The DMA Read Channel has received an error response$/;"	e	enum:__anon7
DMA_ERR_UNSUPPORTED_RQST	include/pedd_dma.h	/^    DMA_ERR_UNSUPPORTED_RQST,$/;"	e	enum:__anon7
DMA_ERR_WR	include/pedd_dma.h	/^    DMA_ERR_WR,         \/**< The DMA Write Channel has received an error$/;"	e	enum:__anon7
DMA_FATAL	include/pedd_hal_dma.h	/^    DMA_FATAL,             \/**< Driver fatal error *\/$/;"	e	enum:__anon43
DMA_INT_ABORT	include/pedd_dma.h	/^    DMA_INT_ABORT       \/**< ABORT interrupt *\/$/;"	e	enum:__anon5
DMA_INT_DONE	include/pedd_dma.h	/^    DMA_INT_DONE = 0,   \/**< DONE interrupt *\/$/;"	e	enum:__anon5
DMA_INT_TYPE	include/pedd_dma.h	/^} DMA_INT_TYPE;$/;"	t	typeref:enum:__anon5
DMA_INVALID_BLOCK_SIZE	include/pedd_hal_dma.h	/^    DMA_INVALID_BLOCK_SIZE,\/**< Invalid block size *\/$/;"	e	enum:__anon43
DMA_INVALID_CHAN	include/pedd_hal_dma.h	/^    DMA_INVALID_CHAN,      \/**< Invalid channel number *\/$/;"	e	enum:__anon43
DMA_INVALID_LL_LEN	include/pedd_hal_dma.h	/^    DMA_INVALID_LL_LEN,    \/**< Invalid linked list length *\/$/;"	e	enum:__anon43
DMA_INVALID_WEIGHT	include/pedd_hal_dma.h	/^    DMA_INVALID_WEIGHT,    \/**< Invalid weight value *\/$/;"	e	enum:__anon43
DMA_INVALID_WM	include/pedd_hal_dma.h	/^    DMA_INVALID_WM,        \/**< Invalid watermark element index *\/$/;"	e	enum:__anon43
DMA_MULTI_BLOCK	include/pedd_dma.h	/^    DMA_MULTI_BLOCK      \/**< Multi block mode *\/$/;"	e	enum:__anon4
DMA_NO_FEED	include/pedd_hal_dma.h	/^    DMA_NO_FEED,           \/**< No new data are feed to linked list *\/$/;"	e	enum:__anon43
DMA_NO_LL	include/pedd_hal_dma.h	/^    DMA_NO_LL,             \/**< No linked list are created *\/$/;"	e	enum:__anon43
DMA_NO_QUEUING_JOBS	include/pedd_hal_dma.h	/^    DMA_NO_QUEUING_JOBS,   \/**< No queuing jobs found *\/$/;"	e	enum:__anon43
DMA_NULL_ARG	include/pedd_hal_dma.h	/^    DMA_NULL_ARG,          \/**< Null arguments are received *\/$/;"	e	enum:__anon43
DMA_READ	include/pedd_dma.h	/^    DMA_READ        \/**< Read *\/$/;"	e	enum:__anon3
DMA_REGS	include/pedd_dma.h	/^struct DMA_REGS {$/;"	s
DMA_RSC	include/pedd_hal_dma.h	/^} DMA_RSC, *PDMA_RSC;$/;"	t	typeref:struct:__anon42
DMA_SINGLE_BLOCK	include/pedd_dma.h	/^    DMA_SINGLE_BLOCK = 0,\/**< Single block mode *\/$/;"	e	enum:__anon4
DMA_SUCCESS	include/pedd_hal_dma.h	/^    DMA_SUCCESS = 0,       \/**< HAL operation succeed *\/$/;"	e	enum:__anon43
DMA_SYNCRUN_CONTEXT	include/pedd_hal_dma.h	/^} DMA_SYNCRUN_CONTEXT, *PDMA_SYNCRUN_CONTEXT;$/;"	t	typeref:struct:__anon44
DMA_UNKNOWN_FAILURE	include/pedd_hal_dma.h	/^    DMA_UNKNOWN_FAILURE,   \/**< Unknown failure *\/$/;"	e	enum:__anon43
DMA_WRITE	include/pedd_dma.h	/^    DMA_WRITE = 0,  \/**< Write *\/$/;"	e	enum:__anon3
DMA_XFER_MODE	include/pedd_dma.h	/^} DMA_XFER_MODE;$/;"	t	typeref:enum:__anon4
DONE	include/pedd_xdata.h	/^        UINT32      DONE      :1;$/;"	m	struct:_XDATA_STATUS::__anon48
DOORBELL	include/pedd_dma.h	/^} DOORBELL;$/;"	t	typeref:union:__anon12
DPRINTF	include/pedd_dfx.h	37;"	d
DRIVER_VERSION	include/pedd.h	19;"	d
DRVER_CLASS_NAME	include/pedd.h	21;"	d
DRVER_NAME	include/pedd.h	20;"	d
DSTR_LEN	include/pedd_dfx.h	40;"	d
DTRACE	include/pedd_dfx.h	29;"	d
DTRACE	include/pedd_dfx.h	34;"	d
DWORD	include/pedd_types.h	/^typedef unsigned int        DWORD;$/;"	t
DarPtrHi	include/pedd_dma.h	/^    UINT32          DarPtrHi;   \/\/ 0x18$/;"	m	struct:__anon26
DarPtrLo	include/pedd_dma.h	/^    UINT32          DarPtrLo;   \/\/ 0x14$/;"	m	struct:__anon26
Data	include/pedd_hal_dma.h	/^    PVOID Data;$/;"	m	struct:__anon44
Data	include/pedd_types.h	/^    UCHAR     Data[4];$/;"	m	struct:_Pci_Data_USER_OUT
Data	include/pedd_types.h	/^    UCHAR    Data[4];$/;"	m	struct:_PciBar_SetDataByOffset_USER_IN
Data	include/pedd_types.h	/^    UCHAR    Data[4];$/;"	m	struct:_PciCfg_SetDataByOffset_USER_IN
DataCheck	include/pedd.h	/^	DMA_DATA_CHECK DataCheck;\/**< Data check status *\/$/;"	m	struct:__anon39
DataCheckDpc	pedd.c	/^void DataCheckDpc(unsigned long arg)$/;"	f
Ddr	include/pedd.h	/^	BOOLEAN Ddr;        \/**< Using DDR memory or not *\/$/;"	m	struct:__anon40
DeviceID	include/pedd_types.h	/^    USHORT  DeviceID;                   \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG
DeviceSpecific	include/pedd_types.h	/^    UCHAR   DeviceSpecific[192];$/;"	m	struct:_PCI_COMMON_CONFIG
Dirc	include/pedd.h	/^	DMA_DIRC Dirc;      \/**< Write or read. *\/$/;"	m	struct:__anon40
Dirc	include/pedd_hal_dma.h	/^    DMA_DIRC Dirc;$/;"	m	struct:__anon44
DmaClrInt	pedd_dma.c	/^void DmaClrInt(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, DMA_INT_TYPE type) {$/;"	f
DmaCtrl	include/pedd_dma.h	/^    DMA_CTRL        DmaCtrl;        \/\/ 0x978$/;"	m	struct:DMA_REGS
DmaDumpLL	pedd_dma.c	/^void DmaDumpLL(PUINT32 llAddr, UINT8 llLen, char *str, int len)$/;"	f
DmaDumpReg	pedd_dma.c	/^void DmaDumpReg(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, char *str, int len)$/;"	f
DmaGetChanNum	pedd_dma.c	/^void DmaGetChanNum(PDMA_REGS pdreg, UINT8 *wrch, UINT8 *rdch) {$/;"	f
DmaGetChanStatus	pedd_dma.c	/^void DmaGetChanStatus(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan,$/;"	f
DmaGetDataEle	pedd_dma.c	/^void DmaGetDataEle(PUINT32 lladdr, UINT8 idx, BOOLEAN *pcs, BOOLEAN *intr,$/;"	f
DmaGetElementPtr	pedd_dma.c	/^void DmaGetElementPtr(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan,$/;"	f
DmaGetLinkEle	pedd_dma.c	/^void DmaGetLinkEle(PUINT32 lladdr, UINT8 idx, BOOLEAN *pcs, PHYADDR *nxt) {$/;"	f
DmaGetXferSize	pedd_dma.c	/^void DmaGetXferSize( PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, UINT32 *size) {$/;"	f
DmaQueryErrSrc	pedd_dma.c	/^BOOLEAN DmaQueryErrSrc(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan,$/;"	f
DmaQueryIntSrc	pedd_dma.c	/^BOOLEAN DmaQueryIntSrc(PDMA_REGS pdreg, DMA_DIRC *dirc, UINT8 *chan,$/;"	f
DmaRegs	include/pedd_hal_dma.h	/^    PDMA_REGS DmaRegs;      \/**< The pointer to DMA registers *\/$/;"	m	struct:__anon42
DmaRsc	include/pedd.h	/^	DMA_RSC DmaRsc;            \/**< DMA resource object *\/$/;"	m	struct:_DEVICE_EXTENSION
DmaRsc	include/pedd_hal_dma.h	/^    PDMA_RSC DmaRsc;$/;"	m	struct:__anon44
DmaSetCtrl	pedd_dma.c	/^void DmaSetCtrl(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, DMA_XFER_MODE mode) {$/;"	f
DmaSetDataEle	pedd_dma.c	/^void DmaSetDataEle(PUINT32 lladdr, UINT8 idx, BOOLEAN pcs, BOOLEAN intr,$/;"	f
DmaSetDoorBell	pedd_dma.c	/^void DmaSetDoorBell(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, BOOLEAN stop) {$/;"	f
DmaSetDst	pedd_dma.c	/^void DmaSetDst( PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, PHYADDR addr ) {$/;"	f
DmaSetLL	pedd_dma.c	/^void DmaSetLL(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, PHYADDR addr) {$/;"	f
DmaSetLLIntErr	pedd_dma.c	/^void DmaSetLLIntErr(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, BOOLEAN loc,$/;"	f
DmaSetLinkEle	pedd_dma.c	/^void DmaSetLinkEle(PUINT32 lladdr, UINT8 idx, BOOLEAN pcs, PHYADDR nxt,$/;"	f
DmaSetMSIAddr	pedd_dma.c	/^void DmaSetMSIAddr(PDMA_REGS pdreg, DMA_DIRC dirc, DMA_INT_TYPE type,$/;"	f
DmaSetMSIData	pedd_dma.c	/^void DmaSetMSIData(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, UINT16 data) {$/;"	f
DmaSetOp	pedd_dma.c	/^void DmaSetOp(PDMA_REGS pdreg, DMA_DIRC dirc, BOOLEAN enb) {$/;"	f
DmaSetSrc	pedd_dma.c	/^void DmaSetSrc( PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, PHYADDR addr ) {$/;"	f
DmaSetWei	pedd_dma.c	/^void DmaSetWei(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, UINT8 wei) {$/;"	f
DmaSetXferSize	pedd_dma.c	/^void DmaSetXferSize(PDMA_REGS pdreg, DMA_DIRC dirc, UINT8 chan, UINT32 size) {$/;"	f
DoneClr	include/pedd_dma.h	/^        UINT32      DoneClr     :8;$/;"	m	struct:__anon16::__anon17
DoneIntrCnt	include/pedd_hal_dma.h	/^    UINT32 DoneIntrCnt;$/;"	m	struct:__anon41
DoneSta	include/pedd_dma.h	/^        UINT32      DoneSta     :8;$/;"	m	struct:__anon14::__anon15
DstPos	include/pedd_hal_dma.h	/^    PHYADDR DstPos;     \/**< The destination address the DMA is working on. *\/$/;"	m	struct:__anon41
DumpLocRam	pedd.c	/^static void DumpLocRam(const PUINT32 addr, UINT32 len, PUINT32 res)$/;"	f	file:
DumpSysMem	pedd.c	/^static void DumpSysMem(const PUINT32 addr, UINT32 len, PUINT32 res)$/;"	f	file:
ENB	include/pedd_dma.h	/^} ENB;$/;"	t	typeref:union:__anon8
EP	include/pedd_xdata.h	/^        UINT32      EP        :1;  \/\/ 15$/;"	m	struct:_XDATA_CTRL::__anon47
ERROR_PRINT	include/pedd_dfx.h	23;"	d
ElPtrHi	include/pedd_dma.h	/^    UINT32          ElPtrHi;    \/\/ 0x20$/;"	m	struct:__anon26
ElPtrLo	include/pedd_dma.h	/^    UINT32          ElPtrLo;    \/\/ 0x1C$/;"	m	struct:__anon26
ElementIdx	include/pedd_hal_dma.h	/^    UINT8 ElementIdx;   \/**< Index of data element the DMA is currently working$/;"	m	struct:__anon41
ElementPos	include/pedd_hal_dma.h	/^    PHYADDR ElementPos; \/**< The element the DMA is currently transferring *\/$/;"	m	struct:__anon41
Enb	include/pedd_dma.h	/^        UINT32      Enb         :1;  \/\/ 0$/;"	m	struct:__anon8::__anon9
Enb	include/pedd_perf.h	/^        UINT32      Enb     :1; \/\/ 5$/;"	m	struct:__anon49::__anon50
End	include/pedd.h	/^	DMA_CHAN_END End;   \/**< Source or destination *\/$/;"	m	struct:__anon40
EpErr	include/pedd_dma.h	/^        UINT32      EpErr       :8;$/;"	m	struct:__anon20::__anon21
Error	include/pedd_hal_dma.h	/^    DMA_ERR Error;      \/**< DMA hardware error if any *\/$/;"	m	struct:__anon41
FALSE	include/pedd_types.h	46;"	d
FLOAT	include/pedd_types.h	/^typedef float               FLOAT;$/;"	t
FeedSize	include/pedd_hal_dma.h	/^    UINT64 FeedSize;    \/**< Total size of DMA transfer. *\/$/;"	m	struct:__anon41
FillLocRam	pedd.c	/^static void FillLocRam(PUINT32 addr, UINT32 len, UINT32 seed, UINT32 incr)$/;"	f	file:
FillSysMem	pedd.c	/^static void FillSysMem(PUINT32 addr, UINT32 len, UINT32 seed, UINT32 incr)$/;"	f	file:
FreeProtocolMem	pedd.c	/^static VOID FreeProtocolMem(struct pedd_dev *priv, UINT32 memSize, PUINT32 *vaddr, dma_addr_t *dma_bus)$/;"	f	file:
GET_CHAN_DST	include/pedd.h	46;"	d
GET_CHAN_SRC	include/pedd.h	41;"	d
GenSrcData	pedd.c	/^static void GenSrcData(PDEVICE_EXTENSION pDevExt, DMA_DIRC dirc, UINT8 chan,$/;"	f	file:
GetBaseDataPAddr	pedd.c	/^static PHYADDR GetBaseDataPAddr(PDEVICE_EXTENSION pDevExt, DMA_DIRC dirc,$/;"	f	file:
GetBaseDataVAddr	pedd.c	/^static PUINT32 GetBaseDataVAddr(PDEVICE_EXTENSION pDevExt, DMA_DIRC dirc,$/;"	f	file:
GetBaseLLPAddr	pedd_hal_dma.c	/^static PHYADDR GetBaseLLPAddr(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan) {$/;"	f	file:
GetBaseLLVAddr	pedd_hal_dma.c	/^static PUINT32 GetBaseLLVAddr(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan) {$/;"	f	file:
HAL_DMA_RET	include/pedd_hal_dma.h	/^} HAL_DMA_RET;$/;"	t	typeref:enum:__anon43
HANDLE	include/pedd_types.h	/^typedef void                *HANDLE;$/;"	t
HW_WAIT	include/pedd_dfx.h	53;"	d
HW_performance_workaround	pedd.c	/^static bool HW_performance_workaround = HW_PERFORMANCE_WORKAROUND;$/;"	v	file:
HalDmaAbort	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaAbort(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan) {$/;"	f
HalDmaDumpLL	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaDumpLL(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan, char *buf) {$/;"	f
HalDmaDumpReg	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaDumpReg(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan,$/;"	f
HalDmaFlushQueue	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaFlushQueue(PDMA_RSC pdrsc) {$/;"	f
HalDmaGetErrInfo	pedd_hal_dma.c	/^char * HalDmaGetErrInfo(HAL_DMA_RET code) {$/;"	f
HalDmaISR	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaISR(PDMA_RSC pdrsc)$/;"	f
HalDmaInit	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaInit(PDMA_RSC pdrsc) {$/;"	f
HalDmaMultiBlockRead	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaMultiBlockRead(PDMA_RSC pdrsc, UINT8 chan, UINT8 lle,$/;"	f
HalDmaMultiBlockWrite	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaMultiBlockWrite(PDMA_RSC pdrsc, UINT8 chan, UINT8 lle,$/;"	f
HalDmaResume	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaResume(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan) {$/;"	f
HalDmaSingleBlockRead	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaSingleBlockRead(PDMA_RSC pdrsc, UINT8 chan, PHYADDR src,$/;"	f
HalDmaSingleBlockWrite	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaSingleBlockWrite(PDMA_RSC pdrsc, UINT8 chan, PHYADDR src,$/;"	f
HalDmaState	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaState(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan,$/;"	f
HalDmaStop	pedd_hal_dma.c	/^HAL_DMA_RET HalDmaStop(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan) {$/;"	f
HeaderType	include/pedd_types.h	/^    UCHAR   HeaderType;                 \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG
High	include/pedd_perf.h	/^        UINT16      High;       \/\/ 32 : 47$/;"	m	struct:__anon53::__anon54
High	include/pedd_perf.h	/^        UINT32      High;       \/\/ 32 : 63$/;"	m	struct:__anon51::__anon52
HighPart	include/pedd_dma.h	/^        UINT32 HighPart;$/;"	m	struct:__anon1::__anon2
IE	include/pedd_xdata.h	/^        UINT32      IE        :1;  \/\/ 17$/;"	m	struct:_XDATA_CTRL::__anon47
INFO_PRINT	include/pedd_dfx.h	28;"	d
INFO_PRINT	include/pedd_dfx.h	33;"	d
INT	include/pedd_types.h	/^typedef int                 INT;$/;"	t
INT16	include/pedd_types.h	/^typedef int16_t			INT16, *PINT16;$/;"	t
INT32	include/pedd_types.h	/^typedef int32_t			INT32, *PINT32;$/;"	t
INT64	include/pedd_types.h	/^typedef int64_t			INT64, *PINT64;$/;"	t
INT8	include/pedd_types.h	/^typedef int8_t			INT8, *PINT8;$/;"	t
INT_CLEAR	include/pedd_dma.h	/^} INT_CLEAR;$/;"	t	typeref:union:__anon16
INT_STATUS	include/pedd_dma.h	/^} INT_STATUS;$/;"	t	typeref:union:__anon14
INT_SYNC_RUN	include/pedd_dfx.h	45;"	d
IS_64	include/pedd_xdata.h	/^        UINT32      IS_64     :1;  \/\/ 14$/;"	m	struct:_XDATA_CTRL::__anon47
IS_WRITE	include/pedd_xdata.h	/^        UINT32      IS_WRITE  :1;  \/\/ 1$/;"	m	struct:_XDATA_CTRL::__anon47
InitErrInfo	pedd_hal_dma.c	/^static void InitErrInfo(void)$/;"	f	file:
InterruptLine	include/pedd_types.h	/^            UCHAR   InterruptLine;      \/\/$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
InterruptPin	include/pedd_types.h	/^            UCHAR   InterruptPin;       \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
IntrObj	include/pedd_hal_dma.h	/^    PVOID IntrObj;          \/**< The interrupt object, OS-specific *\/$/;"	m	struct:__anon42
IoMemPa	include/pedd.h	/^	PHYADDR IoMemPa[16];       \/**< The physical address of buffer on system memory *\/$/;"	m	struct:_DEVICE_EXTENSION
IoMemVa	include/pedd.h	/^	PUINT32 IoMemVa[16];       \/**< The virtual address of buffer on system memory *\/$/;"	m	struct:_DEVICE_EXTENSION
IoctlBufAddr	pedd.c	/^static UINT32 IoctlBufAddr(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlCommand	pedd.c	/^static UINT32 IoctlCommand(struct pedd_dev *priv, PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaAbort	pedd.c	/^static UINT32 IoctlDmaAbort(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaFlushQueue	pedd.c	/^static UINT32 IoctlDmaFlushQueue(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaInit	pedd.c	/^static UINT32 IoctlDmaInit(struct pedd_dev *priv, PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaLLDump	pedd.c	/^static UINT32 IoctlDmaLLDump(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaRW	pedd.c	/^static UINT32 IoctlDmaRW(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaRegsDump	pedd.c	/^static UINT32 IoctlDmaRegsDump(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaResume	pedd.c	/^static UINT32 IoctlDmaResume(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaState	pedd.c	/^static UINT32 IoctlDmaState(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlDmaStop	pedd.c	/^static UINT32 IoctlDmaStop(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlMemDump	pedd.c	/^static UINT32 IoctlMemDump(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlPerf	pedd.c	/^static UINT32 IoctlPerf(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlXPerf	pedd.c	/^static UINT32 IoctlXPerf(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlxDataStartXfer	pedd.c	/^static UINT32 IoctlxDataStartXfer(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlxDataStatus	pedd.c	/^static UINT32 IoctlxDataStatus(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
IoctlxDataStopXfer	pedd.c	/^static UINT32 IoctlxDataStopXfer(PDEVICE_EXTENSION pDevExt, PCMD_INFO pcmd)$/;"	f	file:
Irq	include/pedd_hal_dma.h	/^    INT32 Irq;$/;"	m	struct:__anon42
KERNEL_WAIT	include/pedd_dfx.h	52;"	d
LARGE_INTEGER	include/pedd_types.h	/^} LARGE_INTEGER;$/;"	t	typeref:struct:_LARGE_INTEGER
LENGTH	include/pedd_xdata.h	/^        UINT32      LENGTH    :12; \/\/ 2:13$/;"	m	struct:_XDATA_CTRL::__anon47
LIE	include/pedd_dma.h	/^        UINT32      LIE         :1;    \/\/ 3$/;"	m	struct:__anon22::__anon23
LLEN	include/pedd_dma.h	/^        UINT32      LLEN        :1;    \/\/ 9$/;"	m	struct:__anon22::__anon23
LLElements	include/pedd.h	/^	UINT8 LLElements;   \/**< Numbers of linked list element, including both data$/;"	m	struct:__anon40
LLElements	include/pedd_hal_dma.h	/^    UINT8 LLElements;   \/**< Number of linked list elements *\/$/;"	m	struct:__anon41
LLErr	include/pedd_dma.h	/^        UINT32      LLErr       :8;$/;"	m	struct:__anon18::__anon19
LLP	include/pedd_dma.h	/^        UINT32      LLP         :1;    \/\/ 2$/;"	m	struct:__anon22::__anon23
LLPhyAddr	include/pedd_hal_dma.h	/^    PHYADDR LLPhyAddr[16];  \/**< *\/$/;"	m	struct:__anon42
LLVirAddr	include/pedd_hal_dma.h	/^    PUINT32 LLVirAddr[16];  \/**< *\/$/;"	m	struct:__anon42
LL_ERR_ENB	include/pedd_dma.h	/^} LL_ERR_ENB;$/;"	t	typeref:union:__anon32
LONG	include/pedd_types.h	/^typedef long                LONG;$/;"	t
LONGLONG	include/pedd_types.h	/^typedef long long           LONGLONG;$/;"	t
LPCSTR	include/pedd_types.h	/^typedef const char          *LPCSTR;$/;"	t
LPCWSTR	include/pedd_types.h	/^typedef const WCHAR         *LPCWSTR;$/;"	t
LPDWORD	include/pedd_types.h	/^typedef DWORD               *LPDWORD;$/;"	t
LPSTR	include/pedd_types.h	/^typedef char                *LPSTR;$/;"	t
LPWSTR	include/pedd_types.h	/^typedef WCHAR               *LPWSTR;$/;"	t
LargeInt	include/pedd_perf.h	/^    UINT64 LargeInt;$/;"	m	union:__anon51
LargeInt	include/pedd_perf.h	/^    UINT64 LargeInt;$/;"	m	union:__anon53
LatencyTimer	include/pedd_types.h	/^    UCHAR   LatencyTimer;               \/\/ (ro+)$/;"	m	struct:_PCI_COMMON_CONFIG
Leie	include/pedd_dma.h	/^        UINT32      Leie        :8;     \/\/ 16:23$/;"	m	struct:__anon32::__anon33
Len	include/pedd.h	/^	UINT32 Len;         \/**< Data length for one block transfer *\/$/;"	m	struct:__anon40
Length	include/pedd_types.h	/^    ULONG    Length;$/;"	m	struct:_PciBar_GetDataByOffset_USER_IN
Length	include/pedd_types.h	/^    ULONG    Length;$/;"	m	struct:_PciBar_SetDataByOffset_USER_IN
Length	include/pedd_types.h	/^    ULONG    Length;$/;"	m	struct:_PciCfg_GetDataByOffset_USER_IN
Length	include/pedd_types.h	/^    ULONG    Length;$/;"	m	struct:_PciCfg_SetDataByOffset_USER_IN
Low	include/pedd_perf.h	/^        UINT32      Low;        \/\/ 0 : 31$/;"	m	struct:__anon51::__anon52
Low	include/pedd_perf.h	/^        UINT32      Low;        \/\/ 0 : 31$/;"	m	struct:__anon53::__anon54
LowPart	include/pedd_dma.h	/^        UINT32 LowPart;$/;"	m	struct:__anon1::__anon2
MAX_BLOCK_SIZE	include/pedd_hal_dma.h	27;"	d
MAX_DEVICE	include/pedd.h	22;"	d
MAX_LLELEMENT_NUM	include/pedd_hal_dma.h	35;"	d
MAX_LL_LEN	include/pedd_hal_dma.h	43;"	d
MAX_MSG_SIZE	include/pedd_dfx.h	20;"	d
MAX_WEIGHT	include/pedd_hal_dma.h	47;"	d
MID_COUNTER	include/pedd_perf.h	/^} MID_COUNTER;$/;"	t	typeref:union:__anon53
MIN_BLOCK_SIZE	include/pedd_hal_dma.h	31;"	d
MIN_LLELEMENT_NUM	include/pedd_hal_dma.h	39;"	d
MIN_WEIGHT	include/pedd_hal_dma.h	51;"	d
MSI_only	pedd.c	/^static bool MSI_only = MSI_ONLY;$/;"	v	file:
MaximumLatency	include/pedd_types.h	/^            UCHAR   MaximumLatency;     \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
MinimumGrant	include/pedd_types.h	/^            UCHAR   MinimumGrant;       \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
MsiAddr	include/pedd_hal_dma.h	/^    PHYADDR MsiAddr;        \/**< MSI address *\/$/;"	m	struct:__anon42
MsiData	include/pedd_hal_dma.h	/^    UINT16 MsiData;         \/**< MSI data *\/$/;"	m	struct:__anon42
MultiBlockRW	pedd_hal_dma.c	/^static HAL_DMA_RET MultiBlockRW(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan,$/;"	f	file:
NOADDRINC	include/pedd_xdata.h	/^        UINT32      NOADDRINC :1;  \/\/ 18$/;"	m	struct:_XDATA_CTRL::__anon47
Num	include/pedd_types.h	/^    ULONG    Num;$/;"	m	struct:_PciBar_GetDataByOffset_USER_IN
Num	include/pedd_types.h	/^    ULONG    Num;$/;"	m	struct:_PciBar_SetDataByOffset_USER_IN
Num	include/pedd_types.h	/^    ULONG    Num;$/;"	m	struct:_PciCfg_GetDataByOffset_USER_IN
Num	include/pedd_types.h	/^    ULONG    Num;$/;"	m	struct:_PciCfg_SetDataByOffset_USER_IN
Offset	include/pedd.h	/^	UINT32 Offset;      \/**< Offset to start address of the memory *\/$/;"	m	struct:__anon40
Offset	include/pedd_types.h	/^    ULONG    Offset;$/;"	m	struct:_PciBar_GetDataByOffset_USER_IN
Offset	include/pedd_types.h	/^    ULONG    Offset;$/;"	m	struct:_PciBar_SetDataByOffset_USER_IN
Offset	include/pedd_types.h	/^    ULONG    Offset;$/;"	m	struct:_PciCfg_GetDataByOffset_USER_IN
Offset	include/pedd_types.h	/^    ULONG    Offset;$/;"	m	struct:_PciCfg_SetDataByOffset_USER_IN
PATINC	include/pedd_xdata.h	/^        UINT32      PATINC    :1;  \/\/ 16$/;"	m	struct:_XDATA_CTRL::__anon47
PATTERN	include/pedd_xdata.h	/^   UINT32           PATTERN;   \/\/ 0x10$/;"	m	struct:_XDATA_REGISTERS
PCHAN_INFO	include/pedd_hal_dma.h	/^} CHAN_INFO, *PCHAN_INFO;$/;"	t	typeref:struct:__anon41
PCHAN_INFO_EX	include/pedd.h	/^} CHAN_INFO_EX, *PCHAN_INFO_EX;$/;"	t	typeref:struct:__anon39
PCHAR	include/pedd_types.h	/^typedef char                *PCHAR;$/;"	t
PCIMAXNUM	include/pedd.h	/^	PCIMAXNUM,$/;"	e	enum:__anon34
PCI_ADDRESS_IO_ADDRESS_MASK	include/pedd_types.h	28;"	d
PCI_ADDRESS_IO_SPACE	include/pedd_types.h	24;"	d
PCI_ADDRESS_MEMORY_ADDRESS_MASK	include/pedd_types.h	29;"	d
PCI_ADDRESS_MEMORY_PREFETCHABLE	include/pedd_types.h	26;"	d
PCI_ADDRESS_MEMORY_TYPE_MASK	include/pedd_types.h	25;"	d
PCI_ADDRESS_ROM_ADDRESS_MASK	include/pedd_types.h	30;"	d
PCI_BRIDGE_TYPE	include/pedd_types.h	38;"	d
PCI_CARDBUS_BRIDGE_TYPE	include/pedd_types.h	39;"	d
PCI_COMMON_CONFIG	include/pedd_types.h	/^} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;$/;"	t	typeref:struct:_PCI_COMMON_CONFIG
PCI_DEVICE_TYPE	include/pedd_types.h	37;"	d
PCI_DISABLE_LEVEL_INTERRUPT	include/pedd_types.h	22;"	d
PCI_ENABLE_BUS_MASTER	include/pedd_types.h	14;"	d
PCI_ENABLE_FAST_BACK_TO_BACK	include/pedd_types.h	21;"	d
PCI_ENABLE_IO_SPACE	include/pedd_types.h	12;"	d
PCI_ENABLE_MEMORY_SPACE	include/pedd_types.h	13;"	d
PCI_ENABLE_PARITY	include/pedd_types.h	18;"	d
PCI_ENABLE_SERR	include/pedd_types.h	20;"	d
PCI_ENABLE_SPECIAL_CYCLES	include/pedd_types.h	15;"	d
PCI_ENABLE_VGA_COMPATIBLE_PALETTE	include/pedd_types.h	17;"	d
PCI_ENABLE_WAIT_CYCLE	include/pedd_types.h	19;"	d
PCI_ENABLE_WRITE_AND_INVALIDATE	include/pedd_types.h	16;"	d
PCI_IOCTL_STR_LEN	include/pedd_types.h	149;"	d
PCI_MULTIFUNCTION	include/pedd_types.h	36;"	d
PCI_ROMADDRESS_ENABLED	include/pedd_types.h	41;"	d
PCI_TYPE0_ADDRESSES	include/pedd_types.h	100;"	d
PCI_TYPE1_ADDRESSES	include/pedd_types.h	101;"	d
PCI_TYPE2_ADDRESSES	include/pedd_types.h	102;"	d
PCI_TYPE_20BIT	include/pedd_types.h	33;"	d
PCI_TYPE_32BIT	include/pedd_types.h	32;"	d
PCI_TYPE_64BIT	include/pedd_types.h	34;"	d
PCMD_INFO	include/pedd.h	/^} CMD_INFO, *PCMD_INFO;$/;"	t	typeref:struct:__anon40
PCS	include/pedd_hal_dma.h	/^    UINT8 PCS;          \/**< PCS flag. Used in multi block transfer mode. *\/$/;"	m	struct:__anon41
PDEVICE_EXTENSION	include/pedd.h	/^} DEVICE_EXTENSION, *PDEVICE_EXTENSION;$/;"	t	typeref:struct:_DEVICE_EXTENSION
PDMA_REGS	include/pedd_dma.h	/^typedef struct DMA_REGS *PDMA_REGS;$/;"	t	typeref:struct:DMA_REGS
PDMA_RSC	include/pedd_hal_dma.h	/^} DMA_RSC, *PDMA_RSC;$/;"	t	typeref:struct:__anon42
PDMA_SYNCRUN_CONTEXT	include/pedd_hal_dma.h	/^} DMA_SYNCRUN_CONTEXT, *PDMA_SYNCRUN_CONTEXT;$/;"	t	typeref:struct:__anon44
PEDD	include/pedd.h	/^	PEDD = 0,$/;"	e	enum:__anon34
PEDD_BAR_NUM	include/pedd.h	26;"	d
PEDD_CB	include/pedd_cmd.h	/^}PEDD_CB;$/;"	t	typeref:enum:__anon55
PEDD_CB_BAR_IDX	include/pedd_cmd.h	/^    PEDD_CB_BAR_IDX,$/;"	e	enum:__anon55
PEDD_CB_CHAN_IDX	include/pedd_cmd.h	/^    PEDD_CB_CHAN_IDX,$/;"	e	enum:__anon55
PEDD_CB_CHECK_IDX	include/pedd_cmd.h	/^    PEDD_CB_CHECK_IDX,$/;"	e	enum:__anon55
PEDD_CB_DDR_IDX	include/pedd_cmd.h	/^    PEDD_CB_DDR_IDX,$/;"	e	enum:__anon55
PEDD_CB_DIRC_IDX	include/pedd_cmd.h	/^    PEDD_CB_DIRC_IDX,$/;"	e	enum:__anon55
PEDD_CB_END_IDX	include/pedd_cmd.h	/^    PEDD_CB_END_IDX,$/;"	e	enum:__anon55
PEDD_CB_LB_IDX	include/pedd_cmd.h	/^    PEDD_CB_LB_IDX,$/;"	e	enum:__anon55
PEDD_CB_LEN_IDX	include/pedd_cmd.h	/^    PEDD_CB_LEN_IDX,$/;"	e	enum:__anon55
PEDD_CB_LLE_IDX	include/pedd_cmd.h	/^    PEDD_CB_LLE_IDX,$/;"	e	enum:__anon55
PEDD_CB_NUM_ARGS	include/pedd_cmd.h	/^    PEDD_CB_NUM_ARGS        \/\/ Total numbers$/;"	e	enum:__anon55
PEDD_CB_OFFSET_IDX	include/pedd_cmd.h	/^    PEDD_CB_OFFSET_IDX,$/;"	e	enum:__anon55
PEDD_CB_QUEUE_IDX	include/pedd_cmd.h	/^    PEDD_CB_QUEUE_IDX,$/;"	e	enum:__anon55
PEDD_CB_RECYC_IDX	include/pedd_cmd.h	/^    PEDD_CB_RECYC_IDX,$/;"	e	enum:__anon55
PEDD_CB_REG_IDX	include/pedd_cmd.h	/^    PEDD_CB_REG_IDX,$/;"	e	enum:__anon55
PEDD_CB_SIZE_IDX	include/pedd_cmd.h	/^    PEDD_CB_SIZE_IDX,$/;"	e	enum:__anon55
PEDD_CB_UP_IDX	include/pedd_cmd.h	/^    PEDD_CB_UP_IDX,$/;"	e	enum:__anon55
PEDD_CB_VAL_IDX	include/pedd_cmd.h	/^    PEDD_CB_VAL_IDX,$/;"	e	enum:__anon55
PEDD_CB_WEI_IDX	include/pedd_cmd.h	/^    PEDD_CB_WEI_IDX,$/;"	e	enum:__anon55
PEDD_CB_WM_IDX	include/pedd_cmd.h	/^    PEDD_CB_WM_IDX,$/;"	e	enum:__anon55
PEDD_CDEV_MAJOR	include/pedd.h	23;"	d
PEDD_CTL_CODE	include/pedd_cmd.h	12;"	d
PEDD_DEBUG_	include/pedd_dfx.h	25;"	d
PEDD_DIV64	include/pedd_dfx.h	81;"	d
PEDD_IOCTL_APP_CMD	include/pedd_cmd.h	14;"	d
PEDD_NR_DEVS	include/pedd.h	24;"	d
PEDD_READ_UINT16	include/pedd_dfx.h	59;"	d
PEDD_READ_UINT16_SAFE	include/pedd_dfx.h	60;"	d
PEDD_READ_UINT32	include/pedd_dfx.h	65;"	d
PEDD_READ_UINT8	include/pedd_dfx.h	58;"	d
PEDD_WRITE_UINT16	include/pedd_dfx.h	67;"	d
PEDD_WRITE_UINT16_SAFE	include/pedd_dfx.h	68;"	d
PEDD_WRITE_UINT32	include/pedd_dfx.h	79;"	d
PEDD_WRITE_UINT8	include/pedd_dfx.h	66;"	d
PED_COMMANDS_END	include/ped_ioctl.h	/^	PED_COMMANDS_END,$/;"	e	enum:__anon56
PED_COMMANDS_START	include/ped_ioctl.h	/^	PED_COMMANDS_START           = 0x900,$/;"	e	enum:__anon56
PED_IOCTL_APP_CMD	include/ped_ioctl.h	/^	PED_IOCTL_APP_CMD,$/;"	e	enum:__anon56
PED_IOCTL_PCI_BAR_READ	include/ped_ioctl.h	/^	PED_IOCTL_PCI_BAR_READ,$/;"	e	enum:__anon56
PED_IOCTL_PCI_BRA_WRITE	include/ped_ioctl.h	/^	PED_IOCTL_PCI_BRA_WRITE,$/;"	e	enum:__anon56
PED_IOCTL_PCI_HDR_DATA_READ	include/ped_ioctl.h	/^	PED_IOCTL_PCI_HDR_DATA_READ,$/;"	e	enum:__anon56
PED_IOCTL_PCI_HDR_DATA_WRITE	include/ped_ioctl.h	/^	PED_IOCTL_PCI_HDR_DATA_WRITE,$/;"	e	enum:__anon56
PED_IOCTL_PCI_HDR_READ	include/ped_ioctl.h	/^	PED_IOCTL_PCI_HDR_READ,$/;"	e	enum:__anon56
PED_IOCTL_PING	include/ped_ioctl.h	/^	PED_IOCTL_PING,$/;"	e	enum:__anon56
PERF_CTRL	include/pedd_perf.h	/^} PERF_CTRL;$/;"	t	typeref:union:__anon49
PERF_REGS	include/pedd_perf.h	/^struct PERF_REGS {$/;"	s
PF	include/pedd_dma.h	/^        UINT32      PF          :5;    \/\/ 12:16$/;"	m	struct:__anon22::__anon23
PFLOAT	include/pedd_types.h	/^typedef FLOAT               *PFLOAT;$/;"	t
PHYADDR	include/pedd_dma.h	/^} PHYADDR;$/;"	t	typeref:union:__anon1
PINT16	include/pedd_types.h	/^typedef int16_t			INT16, *PINT16;$/;"	t
PINT32	include/pedd_types.h	/^typedef int32_t			INT32, *PINT32;$/;"	t
PINT64	include/pedd_types.h	/^typedef int64_t			INT64, *PINT64;$/;"	t
PINT8	include/pedd_types.h	/^typedef int8_t			INT8, *PINT8;$/;"	t
PLARGE_INTEGER	include/pedd_types.h	/^typedef LARGE_INTEGER *PLARGE_INTEGER;$/;"	t
PPCI_COMMON_CONFIG	include/pedd_types.h	/^} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;$/;"	t	typeref:struct:_PCI_COMMON_CONFIG
PPERF_REGS	include/pedd_perf.h	/^typedef struct PERF_REGS *PPERF_REGS;$/;"	t	typeref:struct:PERF_REGS
PPciBar_GetDataByOffset_USER_IN	include/pedd_types.h	/^} PciBar_GetDataByOffset_USER_IN, *PPciBar_GetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciBar_GetDataByOffset_USER_IN
PPciBar_SetDataByOffset_USER_IN	include/pedd_types.h	/^} PciBar_SetDataByOffset_USER_IN, *PPciBar_SetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciBar_SetDataByOffset_USER_IN
PPciCfg_GetDataByOffset_USER_IN	include/pedd_types.h	/^} PciCfg_GetDataByOffset_USER_IN, *PPciCfg_GetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciCfg_GetDataByOffset_USER_IN
PPciCfg_GetHeader_USER_OUT	include/pedd_types.h	/^} PciCfg_GetHeader_USER_OUT, *PPciCfg_GetHeader_USER_OUT;$/;"	t	typeref:struct:_PciCfg_GetHeader_USER_OUT
PPciCfg_SetDataByOffset_USER_IN	include/pedd_types.h	/^} PciCfg_SetDataByOffset_USER_IN, *PPciCfg_SetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciCfg_SetDataByOffset_USER_IN
PPci_Data_USER_OUT	include/pedd_types.h	/^} Pci_Data_USER_OUT, *PPci_Data_USER_OUT;$/;"	t	typeref:struct:_Pci_Data_USER_OUT
PRODUCER_FUNC	include/pedd_hal_dma.h	/^typedef BOOLEAN (*PRODUCER_FUNC)(PHYADDR *src, PHYADDR *dst, UINT32 *size,$/;"	t
PSHORT	include/pedd_types.h	/^typedef short               *PSHORT;$/;"	t
PUCHAR	include/pedd_types.h	/^typedef unsigned char       *PUCHAR;$/;"	t
PUINT	include/pedd_types.h	/^typedef unsigned int        *PUINT;$/;"	t
PUINT16	include/pedd_types.h	/^typedef uint16_t		UINT16, *PUINT16;$/;"	t
PUINT32	include/pedd_types.h	/^typedef uint32_t		UINT32, *PUINT32;$/;"	t
PUINT64	include/pedd_types.h	/^typedef uint64_t		UINT64, *PUINT64;$/;"	t
PUINT8	include/pedd_types.h	/^typedef uint8_t			UINT8, *PUINT8;$/;"	t
PULARGE_INTEGER	include/pedd_types.h	/^typedef ULARGE_INTEGER *PULARGE_INTEGER;$/;"	t
PULONG	include/pedd_types.h	/^typedef ULONG               *PULONG;$/;"	t
PULONGLONG	include/pedd_types.h	/^typedef ULONGLONG           *PULONGLONG;$/;"	t
PUSHORT	include/pedd_types.h	/^typedef unsigned short      *PUSHORT;$/;"	t
PVOID	include/pedd_types.h	/^typedef void                *PVOID;$/;"	t
PWD	Makefile	/^	PWD:=$(shell pwd)$/;"	m
PXDATA_CTRL	include/pedd_xdata.h	/^} XDATA_CTRL, *PXDATA_CTRL;$/;"	t	typeref:union:_XDATA_CTRL
PXDATA_REGS	include/pedd_xdata.h	/^} XDATA_REGS, *PXDATA_REGS;$/;"	t	typeref:struct:_XDATA_REGISTERS
PXDATA_RSC	include/pedd_xdata.h	/^} XDATA_RSC, *PXDATA_RSC;$/;"	t	typeref:struct:_XDATA_RSC
PXDATA_STATUS	include/pedd_xdata.h	/^} XDATA_STATUS, *PXDATA_STATUS;$/;"	t	typeref:union:_XDATA_STATUS
ParseCommand	pedd.c	/^static BOOLEAN ParseCommand(CHAR *msg, PCMD_INFO cmdinfo)$/;"	f	file:
Pattern	include/pedd.h	/^	UINT32 Pattern;     	 \/**< Data pattern used by source data generation *\/$/;"	m	struct:__anon39
PatternIncre	include/pedd.h	/^	UINT32 PatternIncre;	 \/**< Increment of data pattern used by source data generation *\/$/;"	m	struct:__anon39
PciBar_GetDataByOffset_USER_IN	include/pedd_types.h	/^} PciBar_GetDataByOffset_USER_IN, *PPciBar_GetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciBar_GetDataByOffset_USER_IN
PciBar_SetDataByOffset_USER_IN	include/pedd_types.h	/^} PciBar_SetDataByOffset_USER_IN, *PPciBar_SetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciBar_SetDataByOffset_USER_IN
PciCfg_GetDataByOffset_USER_IN	include/pedd_types.h	/^} PciCfg_GetDataByOffset_USER_IN, *PPciCfg_GetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciCfg_GetDataByOffset_USER_IN
PciCfg_GetHeader_USER_OUT	include/pedd_types.h	/^} PciCfg_GetHeader_USER_OUT, *PPciCfg_GetHeader_USER_OUT;$/;"	t	typeref:struct:_PciCfg_GetHeader_USER_OUT
PciCfg_SetDataByOffset_USER_IN	include/pedd_types.h	/^} PciCfg_SetDataByOffset_USER_IN, *PPciCfg_SetDataByOffset_USER_IN;$/;"	t	typeref:struct:_PciCfg_SetDataByOffset_USER_IN
Pci_Bar_Read	include/pedd_types.h	/^} Pci_Bar_Read, *pPci_Bar_Read;$/;"	t	typeref:struct:_Pci_Bar_Read
Pci_Bar_Write	include/pedd_types.h	/^} Pci_Bar_Write, *pPci_Bar_Write;$/;"	t	typeref:struct:_Pci_Bar_Write
Pci_Data_USER_OUT	include/pedd_types.h	/^} Pci_Data_USER_OUT, *PPci_Data_USER_OUT;$/;"	t	typeref:struct:_Pci_Data_USER_OUT
Pci_Header_Read	include/pedd_types.h	/^} Pci_Header_Read, *pPci_Header_Read;$/;"	t	typeref:struct:_Pci_Header_Read
Pci_Header_Write	include/pedd_types.h	/^} Pci_Header_Write, *pPci_Header_Write;$/;"	t	typeref:struct:_Pci_Header_Write
PeddProducerFunc	pedd.c	/^static BOOLEAN PeddProducerFunc(PHYADDR *src, PHYADDR *dst,$/;"	f	file:
PeddXferDoneCallback	pedd.c	/^static void PeddXferDoneCallback(DMA_DIRC dirc, UINT8 chan, PVOID ctx)$/;"	f	file:
PerfCtrl	include/pedd_perf.h	/^    PERF_CTRL   PerfCtrl;       \/\/ 0x58$/;"	m	struct:PERF_REGS
PerfGetData	pedd_perf.c	/^BOOLEAN PerfGetData(PPERF_REGS ppfreg, PUINT64 time, PUCHAR tick,$/;"	f
PerfReset	pedd_perf.c	/^void PerfReset(PPERF_REGS ppfreg) {$/;"	f
PerfSetOp	pedd_perf.c	/^void PerfSetOp(PPERF_REGS ppfreg, BOOLEAN enb) {$/;"	f
ProducerContext	include/pedd_hal_dma.h	/^    PVOID ProducerContext;$/;"	m	struct:__anon41
ProducerFunc	include/pedd_hal_dma.h	/^    PRODUCER_FUNC ProducerFunc;$/;"	m	struct:__anon41
ProgIf	include/pedd_types.h	/^    UCHAR   ProgIf;                     \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG
ProtectedAbortXfer	pedd_hal_dma.c	/^static void ProtectedAbortXfer(PDMA_SYNCRUN_CONTEXT context) {$/;"	f	file:
ProtectedCalcXferredSize	pedd_hal_dma.c	/^static void ProtectedCalcXferredSize(PDMA_SYNCRUN_CONTEXT context)  {$/;"	f	file:
ProtectedDumpReg	pedd_hal_dma.c	/^static void ProtectedDumpReg(PDMA_SYNCRUN_CONTEXT context) {$/;"	f	file:
ProtectedGetChanState	pedd_hal_dma.c	/^static void ProtectedGetChanState(PDMA_SYNCRUN_CONTEXT context) {$/;"	f	file:
ProtectedInitMultiBlockXfer	pedd_hal_dma.c	/^static void ProtectedInitMultiBlockXfer(PDMA_SYNCRUN_CONTEXT context) {$/;"	f	file:
ProtectedInitSingleBlockXfer	pedd_hal_dma.c	/^static void ProtectedInitSingleBlockXfer(PDMA_SYNCRUN_CONTEXT context) {$/;"	f	file:
ProtectedSetDoorBell	pedd_hal_dma.c	/^static void ProtectedSetDoorBell(PDMA_SYNCRUN_CONTEXT context) {$/;"	f	file:
QuadPart	include/pedd_dma.h	/^    UINT64 QuadPart;$/;"	m	union:__anon1
QuadPart	include/pedd_types.h	/^    LONGLONG QuadPart;$/;"	m	struct:_LARGE_INTEGER
QuadPart	include/pedd_types.h	/^    ULONGLONG QuadPart;$/;"	m	struct:_ULARGE_INTEGER
Queue	include/pedd.h	/^	BOOLEAN Queue;      \/**< Queue up the request or not *\/$/;"	m	struct:__anon40
RAM_ADDR	include/pedd_xdata.h	/^   UINT32           RAM_ADDR;  \/\/ 0x18$/;"	m	struct:_XDATA_REGISTERS
RAM_PORT	include/pedd_xdata.h	/^   UINT32           RAM_PORT;  \/\/ 0x1c$/;"	m	struct:_XDATA_REGISTERS
RC_SNPS_DEVICE_ID	include/pedd.h	32;"	d
RC_SNPS_VENDOR_ID	include/pedd.h	31;"	d
RD_ERR_HI	include/pedd_dma.h	/^} RD_ERR_HI;$/;"	t	typeref:union:__anon20
RD_ERR_LO	include/pedd_dma.h	/^} WR_ERR, RD_ERR_LO;$/;"	t	typeref:union:__anon18
RIE	include/pedd_dma.h	/^        UINT32      RIE         :1;    \/\/ 4$/;"	m	struct:__anon22::__anon23
RO	include/pedd_dma.h	/^        UINT32      RO          :1;    \/\/ 25$/;"	m	struct:__anon22::__anon23
ROMBaseAddress	include/pedd_types.h	/^            ULONG   ROMBaseAddress;$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
RamPa	include/pedd.h	/^	PHYADDR RamPa;             \/**< The physical address of local RAM *\/$/;"	m	struct:_DEVICE_EXTENSION
RamSize	include/pedd.h	/^	UINT32 RamSize;            \/**< The size of local RAM *\/$/;"	m	struct:_DEVICE_EXTENSION
RamVa	include/pedd.h	/^	PUINT32 RamVa;             \/**< The virtual address of local RAM *\/$/;"	m	struct:_DEVICE_EXTENSION
Rc	include/pedd_types.h	/^    INT      Rc;$/;"	m	struct:_PciCfg_GetDataByOffset_USER_IN
Rc	include/pedd_types.h	/^    INT      Rc;$/;"	m	struct:_PciCfg_SetDataByOffset_USER_IN
RdChInfEx	include/pedd.h	/^	CHAN_INFO_EX RdChInfEx[8]; \/**< The information for all read channels *\/$/;"	m	struct:_DEVICE_EXTENSION
RdChanBytes	include/pedd_perf.h	/^    MID_COUNTER RdChanBytes[8]; \/\/ 0xBC - 0xF8$/;"	m	struct:PERF_REGS
RdChanInfo	include/pedd_hal_dma.h	/^    CHAN_INFO RdChanInfo[8];\/**< The information for all read channels *\/$/;"	m	struct:__anon42
RdChans	include/pedd_dma.h	/^        UINT32      RdChans     :4;  \/\/ 16:19$/;"	m	struct:__anon10::__anon11
RdChans	include/pedd_hal_dma.h	/^    UINT8 RdChans;          \/**< Enabled read channels *\/$/;"	m	struct:__anon42
RdCtrl	include/pedd_dma.h	/^    UINT32          RdCtrl;         \/\/ 0x9A4$/;"	m	struct:DMA_REGS
RdDb	include/pedd_dma.h	/^    DOORBELL        RdDb;           \/\/ 0x9A0$/;"	m	struct:DMA_REGS
RdEnb	include/pedd_dma.h	/^    ENB             RdEnb;          \/\/ 0x99C$/;"	m	struct:DMA_REGS
RdErrStaHi	include/pedd_dma.h	/^    RD_ERR_HI       RdErrStaHi;     \/\/ 0xA28$/;"	m	struct:DMA_REGS
RdErrStaLo	include/pedd_dma.h	/^    RD_ERR_LO       RdErrStaLo;     \/\/ 0xA24$/;"	m	struct:DMA_REGS
RdIntClr	include/pedd_dma.h	/^    INT_CLEAR       RdIntClr;       \/\/ 0xA1C$/;"	m	struct:DMA_REGS
RdIntLLErrEnb	include/pedd_dma.h	/^    LL_ERR_ENB      RdIntLLErrEnb;  \/\/ 0xA34$/;"	m	struct:DMA_REGS
RdIntMsk	include/pedd_dma.h	/^    UINT32          RdIntMsk;       \/\/ 0xA18$/;"	m	struct:DMA_REGS
RdIntSta	include/pedd_dma.h	/^    INT_STATUS      RdIntSta;       \/\/ 0xA10$/;"	m	struct:DMA_REGS
RdMsgAbtAddrHi	include/pedd_dma.h	/^    UINT32          RdMsgAbtAddrHi; \/\/ 0xA48$/;"	m	struct:DMA_REGS
RdMsgAbtAddrLo	include/pedd_dma.h	/^    UINT32          RdMsgAbtAddrLo; \/\/ 0xA44$/;"	m	struct:DMA_REGS
RdMsgData	include/pedd_dma.h	/^    UINT16          RdMsgData[8];   \/\/ 0xA4C - 0xA58 data\/channel$/;"	m	struct:DMA_REGS
RdMsgDonAddrHi	include/pedd_dma.h	/^    UINT32          RdMsgDonAddrHi; \/\/ 0xA40$/;"	m	struct:DMA_REGS
RdMsgDonAddrLo	include/pedd_dma.h	/^    UINT32          RdMsgDonAddrLo; \/\/ 0xA3C$/;"	m	struct:DMA_REGS
RdWeiHi	include/pedd_dma.h	/^    WEIGHT          RdWeiHi;        \/\/ 0x9AC$/;"	m	struct:DMA_REGS
RdWeiLo	include/pedd_dma.h	/^    WEIGHT          RdWeiLo;        \/\/ 0x9A8$/;"	m	struct:DMA_REGS
ReadMTU	include/pedd.h	/^	UINT32 ReadMTU;            \/**< Max PCI packet payload size *\/$/;"	m	struct:_DEVICE_EXTENSION
ReadMTUBits	include/pedd.h	/^	UINT32 ReadMTUBits;$/;"	m	struct:_DEVICE_EXTENSION
Recyc	include/pedd.h	/^	UINT32 Recyc;       \/**< How many times recycle the linked list *\/$/;"	m	struct:__anon40
Recycle	include/pedd_hal_dma.h	/^    UINT32 Recycle;     \/**< How many times to recycle to linked list *\/$/;"	m	struct:__anon41
RegSpacePa	include/pedd.h	/^	PHYADDR RegSpacePa[PEDD_BAR_NUM];$/;"	m	struct:pedd_dev
Reie	include/pedd_dma.h	/^        UINT32      Reie        :8;     \/\/ 0:7$/;"	m	struct:__anon32::__anon33
ResMsg	include/pedd.h	/^	char ResMsg[MAX_MSG_SIZE];\/**< Storage for holding the command response. *\/$/;"	m	struct:__anon40
Reserved0	include/pedd_dma.h	/^        UINT32      Reserved0   :12; \/\/ 4:15$/;"	m	struct:__anon10::__anon11
Reserved0	include/pedd_dma.h	/^        UINT32      Reserved0   :28; \/\/ 3:30$/;"	m	struct:__anon12::__anon13
Reserved0	include/pedd_dma.h	/^        UINT32      Reserved0   :31; \/\/ 1:31$/;"	m	struct:__anon8::__anon9
Reserved0	include/pedd_xdata.h	/^        UINT32      Reserved0 :12; \/\/ 20:31$/;"	m	struct:_XDATA_CTRL::__anon47
Reserved0	include/pedd_xdata.h	/^        UINT32      Reserved0 :15;$/;"	m	struct:_XDATA_STATUS::__anon48
Reserved1	include/pedd_dma.h	/^        UINT32      Reserved1   :12; \/\/ 20:31$/;"	m	struct:__anon10::__anon11
Reserved1	include/pedd_types.h	/^			UCHAR   Reserved1[3];$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
Reserved2	include/pedd_types.h	/^            ULONG   Reserved2;$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
Reset	include/pedd_perf.h	/^        UINT32      Reset   :1; \/\/ 4$/;"	m	struct:__anon49::__anon50
RevisionID	include/pedd_types.h	/^    UCHAR   RevisionID;                 \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG
Rsvd	include/pedd_dma.h	/^        UINT32      Rsvd        :12;    \/\/ 20:31$/;"	m	struct:__anon30::__anon31
Rsvd0	include/pedd_dma.h	/^        UINT32      Rsvd0       :23;    \/\/ 9-31$/;"	m	struct:__anon24::__anon25
Rsvd0	include/pedd_dma.h	/^        UINT32      Rsvd0       :28;    \/\/ 3:30$/;"	m	struct:__anon28::__anon29
Rsvd0	include/pedd_dma.h	/^        UINT32      Rsvd0       :8;     \/\/ 8:15$/;"	m	struct:__anon32::__anon33
Rsvd0	include/pedd_dma.h	/^        UINT32      Rsvd0       :8;$/;"	m	struct:__anon14::__anon15
Rsvd0	include/pedd_dma.h	/^        UINT32      Rsvd0       :8;$/;"	m	struct:__anon16::__anon17
Rsvd0	include/pedd_dma.h	/^        UINT32      Rsvd0       :8;$/;"	m	struct:__anon18::__anon19
Rsvd0	include/pedd_dma.h	/^    UINT32          Rsvd0[2];       \/\/ 0x970 - 0X974$/;"	m	struct:DMA_REGS
Rsvd0	include/pedd_perf.h	/^        UINT16      Rsvd0;      \/\/ 48 : 63$/;"	m	struct:__anon53::__anon54
Rsvd0	include/pedd_perf.h	/^        UINT32      Rsvd0   :4; \/\/ 0 : 3$/;"	m	struct:__anon49::__anon50
Rsvd0	include/pedd_perf.h	/^    UINT32      Rsvd0[12];      \/\/ 0x00 - 0x2C$/;"	m	struct:PERF_REGS
Rsvd1	include/pedd_dma.h	/^        UINT32      Rsvd1       :1;    \/\/ 7$/;"	m	struct:__anon22::__anon23
Rsvd1	include/pedd_dma.h	/^        UINT32      Rsvd1       :8;     \/\/ 24:31$/;"	m	struct:__anon32::__anon33
Rsvd1	include/pedd_dma.h	/^        UINT32      Rsvd1       :8;$/;"	m	struct:__anon14::__anon15
Rsvd1	include/pedd_dma.h	/^        UINT32      Rsvd1       :8;$/;"	m	struct:__anon16::__anon17
Rsvd1	include/pedd_dma.h	/^        UINT32      Rsvd1       :8;$/;"	m	struct:__anon18::__anon19
Rsvd1	include/pedd_dma.h	/^    UINT32          Rsvd1[3];       \/\/ 0x990 - 0x998$/;"	m	struct:DMA_REGS
Rsvd1	include/pedd_perf.h	/^        UINT32      Rsvd1   :24;\/\/ 6 : 29$/;"	m	struct:__anon49::__anon50
Rsvd1	include/pedd_perf.h	/^    UINT32      Rsvd1;          \/\/ 0xFC$/;"	m	struct:PERF_REGS
Rsvd10	include/pedd_dma.h	/^    UINT32          Rsvd10[4];      \/\/ 0xA5C - 0xA68$/;"	m	struct:DMA_REGS
Rsvd11	include/pedd_dma.h	/^    UINT32          Rsvd11[10];$/;"	m	struct:DMA_REGS
Rsvd2	include/pedd_dma.h	/^        UINT32      Rsvd2       :7;    \/\/ 17:23$/;"	m	struct:__anon22::__anon23
Rsvd2	include/pedd_dma.h	/^    UINT32          Rsvd2[3];       \/\/ 0x9B0 - 0x9B8$/;"	m	struct:DMA_REGS
Rsvd3	include/pedd_dma.h	/^    UINT32          Rsvd3;          \/\/ 0x9C0$/;"	m	struct:DMA_REGS
Rsvd4	include/pedd_dma.h	/^    UINT32          Rsvd4[4];       \/\/ 0x9F0 - 0x9FC$/;"	m	struct:DMA_REGS
Rsvd5	include/pedd_dma.h	/^    UINT32          Rsvd5[3];       \/\/ 0xA04 - 0xA0C$/;"	m	struct:DMA_REGS
Rsvd6	include/pedd_dma.h	/^    UINT32          Rsvd6;          \/\/ 0xA14$/;"	m	struct:DMA_REGS
Rsvd7	include/pedd_dma.h	/^    UINT32          Rsvd7;          \/\/ 0xA20$/;"	m	struct:DMA_REGS
Rsvd8	include/pedd_dma.h	/^    UINT32          Rsvd8[2];       \/\/ 0xA2C - 0xA30$/;"	m	struct:DMA_REGS
Rsvd9	include/pedd_dma.h	/^    UINT32          Rsvd9;          \/\/ 0xA38$/;"	m	struct:DMA_REGS
RtlZeroMemory	include/pedd_dfx.h	55;"	d
RxDllp	include/pedd_perf.h	/^    BIG_COUNTER RxDllp;         \/\/ 0x5C - 0x60$/;"	m	struct:PERF_REGS
RxSkipNum	include/pedd_perf.h	/^    BIG_COUNTER RxSkipNum;      \/\/ 0x6C - 0x70$/;"	m	struct:PERF_REGS
RxTlp	include/pedd_perf.h	/^    MID_COUNTER RxTlp;          \/\/ 0x38 - 0x3C$/;"	m	struct:PERF_REGS
RxTlpNum	include/pedd_perf.h	/^    MID_COUNTER RxTlpNum;       \/\/ 0x40 - 0x44$/;"	m	struct:PERF_REGS
SHELL	Makefile	/^SHELL = \/bin\/bash$/;"	m
SHORT	include/pedd_types.h	/^typedef short               SHORT;$/;"	t
SIZE_T	include/pedd_types.h	/^typedef UINT_PTR            SIZE_T;$/;"	t
SN	include/pedd_dma.h	/^        UINT32      SN          :1;    \/\/ 24$/;"	m	struct:__anon22::__anon23
STATUS	include/pedd_xdata.h	/^   XDATA_STATUS     STATUS;    \/\/ 0x14$/;"	m	struct:_XDATA_REGISTERS
STATUS_FAIL	include/pedd_types.h	50;"	d
STATUS_SUCCESS	include/pedd_types.h	49;"	d
STATUS_UNSUCCESSFUL	include/pedd_types.h	51;"	d
SWITCHES	include/pedd_xdata.h	/^   UINT32           SWITCHES;  \/\/ 0x24$/;"	m	struct:_XDATA_REGISTERS
SarPtrHi	include/pedd_dma.h	/^    UINT32          SarPtrHi;   \/\/ 0x10$/;"	m	struct:__anon26
SarPtrLo	include/pedd_dma.h	/^    UINT32          SarPtrLo;   \/\/ 0x0C$/;"	m	struct:__anon26
Sel	include/pedd_dma.h	/^        UINT32      Sel         :1;     \/\/ 31$/;"	m	struct:__anon28::__anon29
SingleBlockRW	pedd_hal_dma.c	/^static HAL_DMA_RET SingleBlockRW(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan,$/;"	f	file:
SrcPos	include/pedd_hal_dma.h	/^    PHYADDR SrcPos;     \/**< The source address the DMA is working on. *\/$/;"	m	struct:__anon41
Status	include/pedd_hal_dma.h	/^    DMA_CHAN_STATUS Status;$/;"	m	struct:__anon41
Status	include/pedd_types.h	/^    USHORT  Status;$/;"	m	struct:_PCI_COMMON_CONFIG
StatusStr	include/pedd_types.h	/^    CHAR                  StatusStr[PCI_IOCTL_STR_LEN];$/;"	m	struct:_PciCfg_GetHeader_USER_OUT
StatusStr	include/pedd_types.h	/^    CHAR     StatusStr[PCI_IOCTL_STR_LEN];$/;"	m	struct:_Pci_Data_USER_OUT
Stop	include/pedd_dma.h	/^        UINT32      Stop        :1;  \/\/ 31$/;"	m	struct:__anon12::__anon13
SubClass	include/pedd_types.h	/^    UCHAR   SubClass;                   \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG
SubSystemID	include/pedd_types.h	/^            USHORT  SubSystemID;$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
SubVendorID	include/pedd_types.h	/^            USHORT  SubVendorID;$/;"	m	struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
TARGET_MODULE_PEDD	Makefile	/^TARGET_MODULE_PEDD:= pedd-bc$/;"	m
TC	include/pedd_dma.h	/^        UINT32      TC          :3;    \/\/ 27:29$/;"	m	struct:__anon22::__anon23
TCB	include/pedd_dma.h	/^        UINT32      TCB         :1;    \/\/ 1$/;"	m	struct:__anon22::__anon23
TD	include/pedd_dma.h	/^        UINT32      TD          :1;    \/\/ 26$/;"	m	struct:__anon22::__anon23
TRIGGER	include/pedd_xdata.h	/^        UINT32      TRIGGER   :1;  \/\/ 19$/;"	m	struct:_XDATA_CTRL::__anon47
TRUE	include/pedd_types.h	45;"	d
Tick	include/pedd_perf.h	/^        UINT32      Tick    :2; \/\/ 30 : 31$/;"	m	struct:__anon49::__anon50
Time	include/pedd_perf.h	/^    BIG_COUNTER Time;           \/\/ 0x30 - 0x34$/;"	m	struct:PERF_REGS
ToErr	include/pedd_dma.h	/^        UINT32      ToErr       :8;$/;"	m	struct:__anon20::__anon21
TotalSize	include/pedd.h	/^	UINT64 TotalSize;   	 \/**< Total transfer size of one request *\/$/;"	m	struct:__anon39
TxDllp	include/pedd_perf.h	/^    BIG_COUNTER TxDllp;         \/\/ 0x64 - 0x68$/;"	m	struct:PERF_REGS
TxSkipNum	include/pedd_perf.h	/^    BIG_COUNTER TxSkipNum;      \/\/ 0x74 - 0x78$/;"	m	struct:PERF_REGS
TxTlp	include/pedd_perf.h	/^    MID_COUNTER TxTlp;          \/\/ 0x48 - 0x4C$/;"	m	struct:PERF_REGS
TxTlpNum	include/pedd_perf.h	/^    MID_COUNTER TxTlpNum;       \/\/ 0x50 - 0x54$/;"	m	struct:PERF_REGS
UCHAR	include/pedd_types.h	/^typedef unsigned char       UCHAR;$/;"	t
UINT	include/pedd_types.h	/^typedef unsigned int        UINT;$/;"	t
UINT16	include/pedd_types.h	/^typedef uint16_t		UINT16, *PUINT16;$/;"	t
UINT32	include/pedd_types.h	/^typedef uint32_t		UINT32, *PUINT32;$/;"	t
UINT64	include/pedd_types.h	/^typedef uint64_t		UINT64, *PUINT64;$/;"	t
UINT8	include/pedd_types.h	/^typedef uint8_t			UINT8, *PUINT8;$/;"	t
UINT_PTR	include/pedd_types.h	/^typedef unsigned long       UINT_PTR;$/;"	t
ULARGE_INTEGER	include/pedd_types.h	/^} ULARGE_INTEGER;$/;"	t	typeref:struct:_ULARGE_INTEGER
ULONG	include/pedd_types.h	/^typedef unsigned long       ULONG;$/;"	t
ULONGLONG	include/pedd_types.h	/^typedef unsigned long long  ULONGLONG;$/;"	t
USHORT	include/pedd_types.h	/^typedef unsigned short      USHORT;$/;"	t
USN	include/pedd_types.h	/^typedef LONGLONG            USN;$/;"	t
UpdateLLElements	pedd_hal_dma.c	/^static HAL_DMA_RET UpdateLLElements(PDMA_RSC pdrsc, DMA_DIRC dirc, UINT8 chan) {$/;"	f	file:
Upstream	include/pedd.h	/^	BOOLEAN Upstream;   \/**< Upstream or downstream. Used by xData only .*\/$/;"	m	struct:__anon40
UrErr	include/pedd_dma.h	/^        UINT32      UrErr       :8;$/;"	m	struct:__anon20::__anon21
VERSION	include/pedd_xdata.h	/^        UINT32      VERSION   :16;$/;"	m	struct:_XDATA_STATUS::__anon48
VFEnb	include/pedd_dma.h	/^        UINT32      VFEnb       :1;     \/\/ 0$/;"	m	struct:__anon24::__anon25
VFunc	include/pedd_dma.h	/^        UINT32      VFunc       :8;     \/\/ 1-8$/;"	m	struct:__anon24::__anon25
VOID	include/pedd_types.h	/^typedef void                VOID;$/;"	t
VendorID	include/pedd_types.h	/^    USHORT  VendorID;                   \/\/ (ro)$/;"	m	struct:_PCI_COMMON_CONFIG
ViwPnt	include/pedd_dma.h	/^        UINT32      ViwPnt      :3;     \/\/ 0:2$/;"	m	struct:__anon28::__anon29
WARNING_PRINT	include/pedd_dfx.h	22;"	d
WCHAR	include/pedd_types.h	/^typedef wchar_t             WCHAR;$/;"	t
WEIGHT	include/pedd_dma.h	/^} WEIGHT;$/;"	t	typeref:union:__anon30
WORD	include/pedd_types.h	/^typedef unsigned short      WORD;$/;"	t
WR_ERR	include/pedd_dma.h	/^} WR_ERR, RD_ERR_LO;$/;"	t	typeref:union:__anon18
WaterMark	include/pedd.h	/^	UINT8 WaterMark;    \/**< Watermark element index *\/$/;"	m	struct:__anon40
WaterMark	include/pedd_hal_dma.h	/^    UINT8 WaterMark;    \/**< Index of watermark element *\/$/;"	m	struct:__anon41
Weight	include/pedd.h	/^	UINT8 Weight;       \/**< The weight of the channel *\/$/;"	m	struct:__anon40
Weight	include/pedd_hal_dma.h	/^    UINT8 Weight;       \/**< The weight of this channel *\/$/;"	m	struct:__anon41
Weight0	include/pedd_dma.h	/^        UINT32      Weight0     :5;     \/\/ 0:4$/;"	m	struct:__anon30::__anon31
Weight1	include/pedd_dma.h	/^        UINT32      Weight1     :5;     \/\/ 5:9$/;"	m	struct:__anon30::__anon31
Weight2	include/pedd_dma.h	/^        UINT32      Weight2     :5;     \/\/ 10:14$/;"	m	struct:__anon30::__anon31
Weight3	include/pedd_dma.h	/^        UINT32      Weight3     :5;     \/\/ 15:19$/;"	m	struct:__anon30::__anon31
WrChInfEx	include/pedd.h	/^	CHAN_INFO_EX WrChInfEx[8]; \/**< The information for all write channels *\/$/;"	m	struct:_DEVICE_EXTENSION
WrChanBytes	include/pedd_perf.h	/^    MID_COUNTER WrChanBytes[8]; \/\/ 0x7C - 0xB8$/;"	m	struct:PERF_REGS
WrChanInfo	include/pedd_hal_dma.h	/^    CHAN_INFO WrChanInfo[8];\/**< The information for all write channels *\/$/;"	m	struct:__anon42
WrChans	include/pedd_dma.h	/^        UINT32      WrChans     :4;  \/\/ 0:3$/;"	m	struct:__anon10::__anon11
WrChans	include/pedd_hal_dma.h	/^    UINT8 WrChans;          \/**< Enabled write channels *\/$/;"	m	struct:__anon42
WrCtrl	include/pedd_dma.h	/^    UINT32          WrCtrl;         \/\/ 0x984$/;"	m	struct:DMA_REGS
WrDb	include/pedd_dma.h	/^    DOORBELL        WrDb;           \/\/ 0x980$/;"	m	struct:DMA_REGS
WrEnb	include/pedd_dma.h	/^    ENB             WrEnb;          \/\/ 0x97C$/;"	m	struct:DMA_REGS
WrErrSta	include/pedd_dma.h	/^    WR_ERR          WrErrSta;       \/\/ 0x9CC$/;"	m	struct:DMA_REGS
WrIntClr	include/pedd_dma.h	/^    INT_CLEAR       WrIntClr;       \/\/ 0x9C8$/;"	m	struct:DMA_REGS
WrIntLLErrEnb	include/pedd_dma.h	/^    LL_ERR_ENB      WrIntLLErrEnb;  \/\/ 0xA00$/;"	m	struct:DMA_REGS
WrIntMsk	include/pedd_dma.h	/^    UINT32          WrIntMsk;       \/\/ 0x9C4$/;"	m	struct:DMA_REGS
WrIntSta	include/pedd_dma.h	/^    INT_STATUS      WrIntSta;       \/\/ 0x9BC$/;"	m	struct:DMA_REGS
WrMsgAbtAddrHi	include/pedd_dma.h	/^    UINT32          WrMsgAbtAddrHi; \/\/ 0x9DC$/;"	m	struct:DMA_REGS
WrMsgAbtAddrLo	include/pedd_dma.h	/^    UINT32          WrMsgAbtAddrLo; \/\/ 0x9D8$/;"	m	struct:DMA_REGS
WrMsgData	include/pedd_dma.h	/^    UINT16          WrMsgData[8];   \/\/ 0x9E0 - 0x9EC data\/channel$/;"	m	struct:DMA_REGS
WrMsgDonAddrHi	include/pedd_dma.h	/^    UINT32          WrMsgDonAddrHi; \/\/ 0x9D4$/;"	m	struct:DMA_REGS
WrMsgDonAddrLo	include/pedd_dma.h	/^    UINT32          WrMsgDonAddrLo; \/\/ 0x9D0$/;"	m	struct:DMA_REGS
WrWeiHi	include/pedd_dma.h	/^    WEIGHT          WrWeiHi;        \/\/ 0x98C$/;"	m	struct:DMA_REGS
WrWeiLo	include/pedd_dma.h	/^    WEIGHT          WrWeiLo;        \/\/ 0x988$/;"	m	struct:DMA_REGS
WriteMTU	include/pedd.h	/^	UINT32 WriteMTU;$/;"	m	struct:_DEVICE_EXTENSION
WriteMTUBits	include/pedd.h	/^	UINT32 WriteMTUBits;$/;"	m	struct:_DEVICE_EXTENSION
XDATA_BUF_DWORD_LEN	include/pedd_xdata.h	23;"	d
XDATA_BUF_SIZE	include/pedd_xdata.h	22;"	d
XDATA_CTRL	include/pedd_xdata.h	/^} XDATA_CTRL, *PXDATA_CTRL;$/;"	t	typeref:union:_XDATA_CTRL
XDATA_ERROR	include/pedd_xdata.h	/^   XDATA_ERROR   = 1,$/;"	e	enum:__anon46
XDATA_OFFSET	pedd.c	100;"	d	file:
XDATA_READ_ADDR_HI	include/pedd_xdata.h	32;"	d
XDATA_READ_ADDR_LO	include/pedd_xdata.h	31;"	d
XDATA_READ_BURSTS	include/pedd_xdata.h	39;"	d
XDATA_READ_BURST_CNT	include/pedd_xdata.h	33;"	d
XDATA_READ_CTRL	include/pedd_xdata.h	34;"	d
XDATA_READ_PATTERN	include/pedd_xdata.h	35;"	d
XDATA_READ_RAM_ADDR	include/pedd_xdata.h	36;"	d
XDATA_READ_RAM_PORT	include/pedd_xdata.h	37;"	d
XDATA_READ_STATUS	include/pedd_xdata.h	30;"	d
XDATA_READ_SWITCHES	include/pedd_xdata.h	38;"	d
XDATA_REGS	include/pedd_xdata.h	/^} XDATA_REGS, *PXDATA_REGS;$/;"	t	typeref:struct:_XDATA_REGISTERS
XDATA_RET	include/pedd_xdata.h	/^} XDATA_RET;$/;"	t	typeref:enum:__anon46
XDATA_RSC	include/pedd_xdata.h	/^} XDATA_RSC, *PXDATA_RSC;$/;"	t	typeref:struct:_XDATA_RSC
XDATA_STATUS	include/pedd_xdata.h	/^} XDATA_STATUS, *PXDATA_STATUS;$/;"	t	typeref:union:_XDATA_STATUS
XDATA_SUCCESS	include/pedd_xdata.h	/^   XDATA_SUCCESS = 0,$/;"	e	enum:__anon46
XDATA_WRITE_ADDR_HI	include/pedd_xdata.h	43;"	d
XDATA_WRITE_ADDR_LO	include/pedd_xdata.h	42;"	d
XDATA_WRITE_BURSTS	include/pedd_xdata.h	50;"	d
XDATA_WRITE_BURST_CNT	include/pedd_xdata.h	44;"	d
XDATA_WRITE_CTRL	include/pedd_xdata.h	45;"	d
XDATA_WRITE_PATTERN	include/pedd_xdata.h	46;"	d
XDATA_WRITE_RAM_ADDR	include/pedd_xdata.h	47;"	d
XDATA_WRITE_RAM_PORT	include/pedd_xdata.h	48;"	d
XDATA_WRITE_STATUS	include/pedd_xdata.h	41;"	d
XDATA_WRITE_SWITCHES	include/pedd_xdata.h	49;"	d
XDRP	include/pedd_xdata.h	28;"	d
XFER_DONE_FUNC	include/pedd_hal_dma.h	/^typedef void (*XFER_DONE_FUNC)(DMA_DIRC dirc, UINT8 chan, PVOID context);$/;"	t
XdRdBytes	include/pedd_perf.h	/^    MID_COUNTER XdRdBytes;      \/\/ 0x108 - 0x10C$/;"	m	struct:PERF_REGS
XdWrBytes	include/pedd_perf.h	/^    MID_COUNTER XdWrBytes;      \/\/ 0x100 - 0x104$/;"	m	struct:PERF_REGS
XferDoneContext	include/pedd_hal_dma.h	/^    PVOID XferDoneContext;  \/**< Context for XferDoneFunc callback *\/$/;"	m	struct:__anon42
XferDoneFunc	include/pedd_hal_dma.h	/^    XFER_DONE_FUNC XferDoneFunc;$/;"	m	struct:__anon42
XferSize	include/pedd_dma.h	/^    UINT32          XferSize;   \/\/ 0x08$/;"	m	struct:__anon26
XferSize	include/pedd_hal_dma.h	/^    UINT32 XferSize;    \/**< The data size have not been xferred in one block.*\/$/;"	m	struct:__anon41
ZERO_MEM	include/pedd_dfx.h	56;"	d
_DEVICE_EXTENSION	include/pedd.h	/^typedef struct _DEVICE_EXTENSION {$/;"	s
_LARGE_INTEGER	include/pedd_types.h	/^typedef struct _LARGE_INTEGER {$/;"	s
_PCI_COMMON_CONFIG	include/pedd_types.h	/^typedef struct _PCI_COMMON_CONFIG $/;"	s
_PCI_HEADER_TYPE_0	include/pedd_types.h	/^        struct _PCI_HEADER_TYPE_0 $/;"	s	union:_PCI_COMMON_CONFIG::__anon45
_PciBar_GetDataByOffset_USER_IN	include/pedd_types.h	/^typedef struct _PciBar_GetDataByOffset_USER_IN {$/;"	s
_PciBar_SetDataByOffset_USER_IN	include/pedd_types.h	/^typedef struct _PciBar_SetDataByOffset_USER_IN {$/;"	s
_PciCfg_GetDataByOffset_USER_IN	include/pedd_types.h	/^typedef struct _PciCfg_GetDataByOffset_USER_IN {$/;"	s
_PciCfg_GetHeader_USER_OUT	include/pedd_types.h	/^typedef struct _PciCfg_GetHeader_USER_OUT {$/;"	s
_PciCfg_SetDataByOffset_USER_IN	include/pedd_types.h	/^typedef struct _PciCfg_SetDataByOffset_USER_IN {$/;"	s
_Pci_Bar_Read	include/pedd_types.h	/^typedef struct _Pci_Bar_Read {$/;"	s
_Pci_Bar_Write	include/pedd_types.h	/^typedef struct _Pci_Bar_Write {$/;"	s
_Pci_Data_USER_OUT	include/pedd_types.h	/^typedef struct _Pci_Data_USER_OUT {$/;"	s
_Pci_Header_Read	include/pedd_types.h	/^typedef struct _Pci_Header_Read {$/;"	s
_Pci_Header_Write	include/pedd_types.h	/^typedef struct _Pci_Header_Write {$/;"	s
_ULARGE_INTEGER	include/pedd_types.h	/^typedef struct _ULARGE_INTEGER {$/;"	s
_XDATA_CTRL	include/pedd_xdata.h	/^typedef union _XDATA_CTRL {$/;"	u
_XDATA_REGISTERS	include/pedd_xdata.h	/^typedef struct _XDATA_REGISTERS{$/;"	s
_XDATA_RSC	include/pedd_xdata.h	/^typedef struct _XDATA_RSC {$/;"	s
_XDATA_STATUS	include/pedd_xdata.h	/^typedef union _XDATA_STATUS {$/;"	u
__PEDD_CMD_H__	include/pedd_cmd.h	8;"	d
__PEDD_DFX_H__	include/pedd_dfx.h	8;"	d
__PEDD_DMA_H__	include/pedd_dma.h	8;"	d
__PEDD_HAL_DMA_H__	include/pedd_hal_dma.h	8;"	d
__PEDD_H__	include/pedd.h	8;"	d
__PEDD_PERF_H__	include/pedd_perf.h	8;"	d
__PEDD_TYPES_H__	include/pedd_types.h	8;"	d
__PEDD_XDATA_H__	include/pedd_xdata.h	8;"	d
__PED_IOCTL_H__	include/ped_ioctl.h	8;"	d
__lux_parse_cmd_t	include/pedd_cmd.h	/^typedef struct __lux_parse_cmd_t$/;"	s
__lux_parse_t	include/pedd_cmd.h	/^typedef struct __lux_parse_t$/;"	s
arg	include/pedd_cmd.h	/^   char            *arg;          \/* arg name *\/$/;"	m	struct:__lux_parse_cmd_t
args	include/pedd_cmd.h	/^   lux_parse_cmd_t  *args;    \/* array of valid args *\/$/;"	m	struct:__lux_parse_t
b_64D	include/pedd_dma.h	/^        UINT32      b_64D       :1;    \/\/ 11$/;"	m	struct:__anon22::__anon23
b_64S	include/pedd_dma.h	/^        UINT32      b_64S       :1;    \/\/ 10$/;"	m	struct:__anon22::__anon23
bar	include/pedd.h	/^	void * __iomem bar[PEDD_BAR_NUM];$/;"	m	struct:pedd_dev
bar_len	include/pedd.h	/^	unsigned long bar_len[PEDD_BAR_NUM];$/;"	m	struct:pedd_dev
cdev	include/pedd.h	/^	struct cdev cdev;$/;"	m	struct:pedd_dev	typeref:struct:pedd_dev::cdev
default_val	include/pedd_cmd.h	/^   ULONG           default_val;   \/* default val if arg not on commandline *\/$/;"	m	struct:__lux_parse_cmd_t
device_id	include/pedd.h	/^	uint16_t device_id;$/;"	m	struct:pedd_dev
devno	include/pedd.h	/^	dev_t devno;$/;"	m	struct:pedd_dev
dma_bus	include/pedd.h	/^	dma_addr_t dma_bus[16];$/;"	m	struct:_DEVICE_EXTENSION
eDMA	pedd.c	/^static short int eDMA = EDMA;$/;"	v	file:
eDMA_mem_bar	pedd.c	/^static short int eDMA_mem_bar = EDMA_MEM_BAR;$/;"	v	file:
eDMA_regs_bar	pedd.c	/^static short int eDMA_regs_bar = EDMA_REGS_BAR;$/;"	v	file:
eDMA_regs_off	pedd.c	/^static long eDMA_regs_off = EDMA_REGS_OFF;$/;"	v	file:
gErrInfo	pedd_hal_dma.c	/^static char *gErrInfo[DMA_ERR_CODE_NUM] = {0};$/;"	v	file:
got_regions	include/pedd.h	/^	int got_regions;$/;"	m	struct:pedd_dev
in_use	include/pedd.h	/^	int in_use;$/;"	m	struct:pedd_dev
ioctl_in	include/pedd_types.h	/^	PciBar_GetDataByOffset_USER_IN ioctl_in;$/;"	m	struct:_Pci_Bar_Read
ioctl_in	include/pedd_types.h	/^	PciBar_SetDataByOffset_USER_IN ioctl_in;$/;"	m	struct:_Pci_Bar_Write
ioctl_in	include/pedd_types.h	/^	PciCfg_GetDataByOffset_USER_IN ioctl_in;$/;"	m	struct:_Pci_Header_Read
ioctl_in	include/pedd_types.h	/^	PciCfg_SetDataByOffset_USER_IN ioctl_in;$/;"	m	struct:_Pci_Header_Write
ioctl_out	include/pedd_types.h	/^	Pci_Data_USER_OUT ioctl_out;$/;"	m	struct:_Pci_Bar_Read
ioctl_out	include/pedd_types.h	/^	Pci_Data_USER_OUT ioctl_out;$/;"	m	struct:_Pci_Bar_Write
ioctl_out	include/pedd_types.h	/^	Pci_Data_USER_OUT ioctl_out;$/;"	m	struct:_Pci_Header_Read
ioctl_out	include/pedd_types.h	/^	Pci_Data_USER_OUT ioctl_out;$/;"	m	struct:_Pci_Header_Write
irq	include/pedd.h	/^	int irq;$/;"	m	struct:pedd_dev
irq_count	include/pedd.h	/^	uint32_t irq_count;$/;"	m	struct:pedd_dev
irq_line	include/pedd.h	/^	uint8_t irq_line;$/;"	m	struct:pedd_dev
irq_pin	include/pedd.h	/^	uint8_t irq_pin;$/;"	m	struct:pedd_dev
isdigit	include/pedd_cmd.h	16;"	d
islower	include/pedd_cmd.h	17;"	d
isxdigit	include/pedd_cmd.h	20;"	d
lux_parse_cmd_args	pedd_cmd.c	/^int lux_parse_cmd_args(lux_parse_t *arg_set, char *cmdline, char *cmd,$/;"	f
lux_parse_cmd_t	include/pedd_cmd.h	/^} lux_parse_cmd_t;$/;"	t	typeref:struct:__lux_parse_cmd_t
lux_parse_t	include/pedd_cmd.h	/^} lux_parse_t;$/;"	t	typeref:struct:__lux_parse_t
mmio_addr	include/pedd.h	/^	void *mmio_addr;$/;"	m	struct:pedd_dev
mmio_len	include/pedd.h	/^	unsigned long mmio_len;$/;"	m	struct:pedd_dev
mmio_start	include/pedd.h	/^	void *mmio_start;$/;"	m	struct:pedd_dev
ncmds	include/pedd_cmd.h	/^   ULONG            ncmds;    \/* number of valid args *\/$/;"	m	struct:__lux_parse_t
open_flag	include/pedd.h	/^	int open_flag;$/;"	m	struct:pedd_dev
pPci_Bar_Read	include/pedd_types.h	/^} Pci_Bar_Read, *pPci_Bar_Read;$/;"	t	typeref:struct:_Pci_Bar_Read
pPci_Bar_Write	include/pedd_types.h	/^} Pci_Bar_Write, *pPci_Bar_Write;$/;"	t	typeref:struct:_Pci_Bar_Write
pPci_Header_Read	include/pedd_types.h	/^} Pci_Header_Read, *pPci_Header_Read;$/;"	t	typeref:struct:_Pci_Header_Read
pPci_Header_Write	include/pedd_types.h	/^} Pci_Header_Write, *pPci_Header_Write;$/;"	t	typeref:struct:_Pci_Header_Write
pciData	include/pedd_types.h	/^    PCI_COMMON_CONFIG     pciData;$/;"	m	struct:_PciCfg_GetHeader_USER_OUT
pci_dma_h	include/pedd.h	50;"	d
pci_dma_l	include/pedd.h	52;"	d
pdev	include/pedd.h	/^	struct pci_dev	*pdev;$/;"	m	struct:pedd_dev	typeref:struct:pedd_dev::pci_dev
pedd_Read_Header	pedd.c	/^void pedd_Read_Header(struct pci_dev *pdev, PCI_COMMON_CONFIG *data)$/;"	f
pedd_cb	pedd_cmd.c	/^static lux_parse_t pedd_cb = {$/;"	v	file:
pedd_cb_args	pedd_cmd.c	/^static lux_parse_cmd_t pedd_cb_args[PEDD_CB_NUM_ARGS] = {$/;"	v	file:
pedd_cdev_init	pedd.c	/^static int pedd_cdev_init(struct pedd_dev *peddev)$/;"	f	file:
pedd_cdev_major	pedd.c	/^int pedd_cdev_major = PEDD_CDEV_MAJOR;$/;"	v
pedd_cdev_minor	pedd.c	/^int pedd_cdev_minor = 0;$/;"	v
pedd_cleanup_module	pedd.c	/^module_exit(pedd_cleanup_module);$/;"	v
pedd_cleanup_module	pedd.c	/^static void __exit pedd_cleanup_module(void)$/;"	f	file:
pedd_dev	include/pedd.h	/^struct pedd_dev {$/;"	s
pedd_devices	pedd.c	/^struct pedd_dev *pedd_devices = NULL;$/;"	v	typeref:struct:pedd_dev
pedd_devno	pedd.c	/^dev_t pedd_devno;$/;"	v
pedd_ext	include/pedd.h	/^	DEVICE_EXTENSION pedd_ext;$/;"	m	struct:pedd_dev
pedd_fops	pedd.c	/^static struct file_operations pedd_fops = {$/;"	v	typeref:struct:file_operations	file:
pedd_init_module	pedd.c	/^module_init(pedd_init_module);$/;"	v
pedd_init_module	pedd.c	/^static int __init pedd_init_module(void)$/;"	f	file:
pedd_ioctl	pedd.c	/^static long pedd_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)$/;"	f	file:
pedd_isr	pedd.c	/^static irqreturn_t pedd_isr(int irq, void *dev_id)$/;"	f	file:
pedd_map_bars	pedd.c	/^static int pedd_map_bars(struct pedd_dev *priv, struct pci_dev *pdev)$/;"	f	file:
pedd_nr_devs	pedd.c	/^int pedd_nr_devs    = PEDD_NR_DEVS;$/;"	v
pedd_open	pedd.c	/^static int pedd_open(struct inode *inode, struct file *filp)$/;"	f	file:
pedd_parse_cmd	pedd_cmd.c	/^int pedd_parse_cmd(char *cmdline, char *cmd, unsigned long *arg_vals)$/;"	f
pedd_pci_driver	pedd.c	/^static struct pci_driver pedd_pci_driver = {$/;"	v	typeref:struct:pci_driver	file:
pedd_pci_tbl	pedd.c	/^static const struct pci_device_id pedd_pci_tbl[] = {$/;"	v	typeref:struct:pci_device_id	file:
pedd_priv_exit	pedd.c	/^static void pedd_priv_exit(struct pedd_dev *priv)$/;"	f	file:
pedd_priv_init	pedd.c	/^static void pedd_priv_init(struct pedd_dev *priv)$/;"	f	file:
pedd_probe	pedd.c	/^static int pedd_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id)$/;"	f	file:
pedd_read	pedd.c	/^static ssize_t pedd_read(struct file *filp, char __user *buf, size_t count,$/;"	f	file:
pedd_release	pedd.c	/^static int pedd_release(struct inode *inode, struct file *filp)$/;"	f	file:
pedd_remove	pedd.c	/^static void pedd_remove(struct pci_dev *pdev)$/;"	f	file:
pedd_rw_pci_bar	pedd.c	/^void pedd_rw_pci_bar(INT d, UINT32 length, void *bar_addr, UINT32 offset, UCHAR *val)$/;"	f
pedd_rw_pci_cfg	pedd.c	/^void pedd_rw_pci_cfg(struct pci_dev *pdev, INT d, UINT32 length, UINT32 offset, UCHAR *val)$/;"	f
pedd_rw_pci_hdr	pedd.c	/^int pedd_rw_pci_hdr(struct pci_dev *pdev, INT rc, INT d, UINT32 length, UINT32 offset, UCHAR *val)$/;"	f
pedd_unmap_bars	pedd.c	/^static void pedd_unmap_bars(struct pedd_dev *priv, struct pci_dev *pdev)$/;"	f	file:
pedd_write	pedd.c	/^static ssize_t pedd_write(struct file *filp, const char __user *buf,$/;"	f	file:
revision	include/pedd.h	/^	uint8_t revision;$/;"	m	struct:pedd_dev
rsvd	include/pedd_xdata.h	/^   UINT32           rsvd;      \/\/ 0x20 (was LED ctrl on old board)$/;"	m	struct:_XDATA_REGISTERS
startDownstreamRead	pedd_xdata.c	/^static int startDownstreamRead( void * rsc_)$/;"	f	file:
startDownstreamRead	pedd_xdata.c	/^static void startDownstreamRead( PXDATA_RSC rsc)$/;"	f	file:
startDownstreamWrite	pedd_xdata.c	/^static int startDownstreamWrite( void *rsc_)$/;"	f	file:
startDownstreamWrite	pedd_xdata.c	/^static void startDownstreamWrite( PXDATA_RSC rsc)$/;"	f	file:
startDownstreamXfer	pedd_xdata.c	/^static XDATA_RET startDownstreamXfer(PXDATA_RSC rsc, BOOLEAN isWrite,$/;"	f	file:
startUpstreamXfer	pedd_xdata.c	/^static XDATA_RET startUpstreamXfer( PXDATA_RSC rsc, BOOLEAN isWrite,$/;"	f	file:
status	include/pedd_types.h	/^    ULONG                 status;$/;"	m	struct:_PciCfg_GetHeader_USER_OUT
status	include/pedd_types.h	/^    ULONG    status;$/;"	m	struct:_PciCfg_SetDataByOffset_USER_IN
status	include/pedd_types.h	/^    ULONG    status;$/;"	m	struct:_Pci_Data_USER_OUT
sub_system_id	include/pedd.h	/^	uint16_t sub_system_id;$/;"	m	struct:pedd_dev
sub_vendor_id	include/pedd.h	/^	uint16_t sub_vendor_id;$/;"	m	struct:pedd_dev
synopsys_pci_t	include/pedd.h	/^} synopsys_pci_t;$/;"	t	typeref:enum:__anon34
tick_count_start	include/pedd.h	/^	UINT64 tick_count_start;$/;"	m	struct:__anon39
tick_count_stop	include/pedd.h	/^	UINT64 tick_count_stop;$/;"	m	struct:__anon39
tlet	include/pedd.h	/^	struct tasklet_struct tlet;$/;"	m	struct:pedd_dev	typeref:struct:pedd_dev::tasklet_struct
topdir	Makefile	/^topdir := $(shell cd $(src)\/.. && pwd)$/;"	m
toupper	include/pedd_cmd.h	18;"	d
ts_read	pedd_xdata.c	/^static struct task_struct *ts_read;$/;"	v	typeref:struct:task_struct	file:
ts_write	pedd_xdata.c	/^static struct task_struct *ts_write;$/;"	v	typeref:struct:task_struct	file:
type0	include/pedd_types.h	/^        } type0;$/;"	m	union:_PCI_COMMON_CONFIG::__anon45	typeref:struct:_PCI_COMMON_CONFIG::__anon45::_PCI_HEADER_TYPE_0
u	include/pedd_types.h	/^    } u;$/;"	m	struct:_PCI_COMMON_CONFIG	typeref:union:_PCI_COMMON_CONFIG::__anon45
vendor_id	include/pedd.h	/^	uint16_t vendor_id;$/;"	m	struct:pedd_dev
xData	pedd.c	/^static short int xData = XDATA;$/;"	v	file:
xDataBus	include/pedd_xdata.h	/^    dma_addr_t       xDataBus;$/;"	m	struct:_XDATA_RSC
xDataDownstreamRun	include/pedd_xdata.h	/^    BOOLEAN          xDataDownstreamRun;\/**< xData downstream work flag  *\/$/;"	m	struct:_XDATA_RSC
xDataHalt	pedd_xdata.c	/^static void xDataHalt( PXDATA_RSC rsc, BOOLEAN nocomplain, char *ResMsg )$/;"	f	file:
xDataInit	pedd_xdata.c	/^XDATA_RET xDataInit( PXDATA_RSC rsc, UINT32 ReadMTU, UINT32 WriteMTU )$/;"	f
xDataLocMemPa	include/pedd_xdata.h	/^    PHYADDR          xDataLocMemPa;     \/**< xData local buffer phy addr *\/$/;"	m	struct:_XDATA_RSC
xDataLocMemSize	include/pedd_xdata.h	/^    UINT32           xDataLocMemSize;   \/**< xData local buffer size *\/$/;"	m	struct:_XDATA_RSC
xDataLocMemVa	include/pedd_xdata.h	/^    PUINT32          xDataLocMemVa;     \/**< xData local buffer virtual addr *\/$/;"	m	struct:_XDATA_RSC
xDataMaxReadLen	include/pedd_xdata.h	/^    UINT32           xDataMaxReadLen;   \/**< xData max xfer burst len *\/$/;"	m	struct:_XDATA_RSC
xDataMaxWriteLen	include/pedd_xdata.h	/^    UINT32           xDataMaxWriteLen;  \/**< xData max xfer burst len *\/$/;"	m	struct:_XDATA_RSC
xDataMemPa	include/pedd_xdata.h	/^    PHYADDR          xDataMemPa;        \/**< xData system buffer phy addr *\/$/;"	m	struct:_XDATA_RSC
xDataMemSize	include/pedd_xdata.h	/^    UINT32           xDataMemSize;      \/**< xData buffer size *\/$/;"	m	struct:_XDATA_RSC
xDataMemVa	include/pedd_xdata.h	/^    PUINT32          xDataMemVa;        \/**< xData system buffer virtual addr *\/$/;"	m	struct:_XDATA_RSC
xDataRegs	include/pedd_xdata.h	/^    PVOID            xDataRegs;         \/**< xData control regs *\/$/;"	m	struct:_XDATA_RSC
xDataRsc	include/pedd.h	/^	XDATA_RSC xDataRsc;        \/**< Extra Data parameters *\/$/;"	m	struct:_DEVICE_EXTENSION
xDataStartXfer	pedd_xdata.c	/^XDATA_RET xDataStartXfer( PXDATA_RSC rsc, BOOLEAN isWrite, BOOLEAN isUpstream,$/;"	f
xDataStatus	pedd_xdata.c	/^XDATA_RET xDataStatus( PXDATA_RSC rsc, char *ResMsg )$/;"	f
xDataStopXfer	pedd_xdata.c	/^XDATA_RET xDataStopXfer( PXDATA_RSC rsc, BOOLEAN isUpstream, char *ResMsg )$/;"	f
xData_bar	pedd.c	/^static short int xData_bar = XDATA_BAR;$/;"	v	file:
