Verification Engineer

Aliso Viejo, CA

The Verification Engineer’s primary job function is to work with other team members to develop test plans and verify the RTL designs.

Requirements:

  • B.S. or M.S. in Electrical Engineering or equivalent
  • 5 to 10 years of design verification experience
  • Experience with verification of modules from test plan to regression
  • Knowledge of Verilog, SystemVerilog, UVM, and Synopsys VCS

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Accepted formats: PDF, Word Doc

Accepted formats: PDF, Word Doc