The Digital Design Engineer’s primary job function is to work with other team members to design and develop the digital modules from the concept to tape out or release for FPGA prototype.
1. B.S. or M.S. in Electrical Engineering or equivalent
2. 5 to 10 years of RTL design experience
3. Experience with the full design cycle for ASICs or FPGAs.
4. Knowledge of Verilog, SystemVerilog, and Synopsys VCS
Please fill out the form below to submit your application.